{"width":"100%","url":"https://atsk.hatenadiary.org/entry/20080903/1220457843","title":" Verilog-HDL \u52c9\u5f37\u7528","author_name":"atsk","categories":["HW","\u30e1\u30e2"],"published":"2008-09-03 01:04:03","version":"1.0","provider_name":"Hatena Blog","blog_url":"https://atsk.hatenadiary.org/","provider_url":"https://hatena.blog","height":"190","blog_title":"\u9b3c\u3001\u3082\u3057\u304f\u306f\u4f8d\uff1f","description":"Modelsim Xilinx Edition (\u7121\u511f\u7248 Modelsim \u3067\u3042\u308b\u30b9\u30bf\u30fc\u30bf\u30fc\u304c\u542b\u307e\u308c\u308b) \u3068 ISE WebPack \u304c Download \u3067\u304d\u308b\u30da\u30fc\u30b8\uff1ahttp://japan.xilinx.com/support/download/index.htm ARM \u958b\u767a\u74b0\u5883\u3092\u7121\u6599\u3067\u6574\u3048\u308b\u65b9\u6cd5\u3092\u307e\u3068\u3081\u3066\u304f\u308c\u3066\u3044\u308b\u30b5\u30a4\u30c8\uff1ahttp://www.neko.ne.jp/~freewing/cpu/arm_gcc/ JTAG \u30c0\u30a6\u30f3\u30ed\u30fc\u30c9\u30b1\u30fc\u30d6\u30eb\u3092\u500b\u4eba\u3067\u8cb7\u3048\u305d\u3046\u306a\u30da\u30fc\u30b8\uff1ahttp://www.hdl.co.jp/tuhan/ptuhan_2.html \u4ee5\u4e0a\u306e\u30da\u30fc\u30b8\u3067\u5fc5\u8981\u7269\u3092\u305d\u308d\u3048\u308b\u3068\u3001\u3042\u3068\u2026","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fatsk.hatenadiary.org%2Fentry%2F20080903%2F1220457843\" title=\" Verilog-HDL \u52c9\u5f37\u7528 - \u9b3c\u3001\u3082\u3057\u304f\u306f\u4f8d\uff1f\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","author_url":"https://blog.hatena.ne.jp/atsk/","image_url":null,"type":"rich"}