{"html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fblog-e.uosoft.net%2Fentry%2F20100112%2F1263222851\" title=\"FPGA\u3067\u904a\u3076\u3068\u304d\u306e\u30e1\u30e2 - \u96fb\u5b50\u8da3\u5473\u306e\u90e8\u5c4b\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","provider_url":"https://hatena.blog","published":"2010-01-12 00:14:11","blog_url":"https://blog-e.uosoft.net/","height":"190","version":"1.0","provider_name":"Hatena Blog","author_name":"uosoft","description":"\u4e45\u3057\u3076\u308a\u306b\u4ee5\u524d\u306e\u30a8\u30f3\u30c8\u30ea\u30fc\u300cFPGA\u306e\u3053\u3068\u300d\u3067\u3082\u7d39\u4ecb\u3057\u305fMAX II\u30de\u30a4\u30af\u30ed\u30ad\u30c3\u30c8\u3067\u904a\u307c\u3046\u3068\u3057\u305f\u3089\u8272\u3005\u3068\u5fd8\u308c\u3066\u305f\u306e\u3067\u3001\u8efd\u304f\u30e1\u30e2\u3092\u66f8\u304d\u307e\u3059\u3002\u74b0\u5883\u306f Quartus II 9.1 \u3067\u3059\u3002 \u65b0\u898f\u306b\u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u3092\u4f5c\u3063\u305f\u3089\u3001\u307e\u305a\u30c7\u30d0\u30a4\u30b9\u306e\u8a2d\u5b9a \u30c7\u30d0\u30a4\u30b9\u306f EPM2210F324C3 \u3092\u9078\u629e\u3059\u308b \u30d4\u30f3\u914d\u7f6e\u306e\u8a2d\u5b9a \"Assignment Editer\"\u3067\u30d4\u30f3\u306e\u30a2\u30b5\u30a4\u30f3\u3092\u884c\u3046\u3002 \u4ee5\u4e0b\u306e\u753b\u50cf\u306fMAX II\u30de\u30a4\u30af\u30ed\u30ad\u30c3\u30c8\u306e\u57fa\u672cI/O\u3092\u5b9a\u7fa9\u3057\u3066\u3044\u308b\u306e\u3067\u3001\u30c6\u30f3\u30d7\u30ec\u30fc\u30c8\u3068\u3057\u3066\u6bce\u56de\u540c\u3058\u8a2d\u5b9a\u3092\u3057\u3066\u3044\u307e\u3059\u3002\u3067\u3059\u3002 \u30bd\u30fc\u30b9\u30b3\u30fc\u30c9\u30d5\u30a1\u30a4\u30eb\u3092\u8ffd\u52a0 Velilog HDL File(*.v)\u3092\u8ffd\u52a0\u3057\u3066\u3001\u30bd\u30fc\u30b9\u30b3\u30fc\u30c9\u3092\u8a18\u8ff0\u3059\u308b\u3002 \u4ee5\u4e0b\u2026","width":"100%","url":"https://blog-e.uosoft.net/entry/20100112/1263222851","title":"FPGA\u3067\u904a\u3076\u3068\u304d\u306e\u30e1\u30e2","author_url":"https://blog.hatena.ne.jp/uosoft/","blog_title":"\u96fb\u5b50\u8da3\u5473\u306e\u90e8\u5c4b","type":"rich","image_url":"https://cdn-ak.f.st-hatena.com/images/fotolife/u/uosoft/20100111/20100111131755.jpg","categories":["FPGA","\u96fb\u5b50\u5de5\u4f5c"]}