{"title":"Verilog \u306e\u6f14\u7b97\u6642\u306e\u5e45\u62e1\u5f35\u3067\u3057\u304f\u3058\u3063\u305f\u8a71","type":"rich","width":"100%","published":"2024-05-23 12:53:28","blog_title":"Ryuz's tech blog","description":"\u306a\u306b\u304c\u8d77\u304d\u305f\u306e\u304b \u4e0b\u8a18\u306e\u3088\u3046\u306a\u30b7\u30fc\u30f3\u3067\u4f55\u3084\u3089 Verilator \u304c Operator NOT expects 5 bits on the LHS, but LHS's VARREF 'b' generates 4 bits. \u3068\u3044\u3046\u30ef\u30fc\u30cb\u30f3\u30b0\u3092\u51fa\u3057\u3066\u304d\u305f\u3002 logic [3:0] a; logic [3:0] b; logic [4:0] c; assign c = a + ~b; 4bit\u540c\u58eb\u306e\u52a0\u7b97\u30925bit \u306b\u5165\u308c\u308b\u306e\u3067\u4f55\u306e\u554f\u984c\u3082\u7121\u304b\u308d\u3046\u3068\u601d\u3063\u3066\u3044\u305f\u3089\u3001\u554f\u984c\u3042\u308a\u3042\u308a\u3060\u3063\u305f\u3068\u3044\u3046\u8a71\u3067\u3059\u3002 \u3069\u3046\u3044\u3046\u3053\u3068\u304b \u4e0b\u8a18\u306e\u3088\u3046\u306a\u30b3\u30fc\u30c9\u3060\u3068\u5c11\u3057\u308f\u304b\u308a\u3084\u3059\u3044\u304b\u3068\u601d\u3044\u307e\u3059\u3002 logic [3:0] a = \u2026","provider_url":"https://hatena.blog","categories":["FPGA"],"url":"https://blog.rtc-lab.com/entry/2024/05/23/125328","blog_url":"https://blog.rtc-lab.com/","version":"1.0","author_url":"https://blog.hatena.ne.jp/Ryuz88/","author_name":"Ryuz88","provider_name":"Hatena Blog","height":"190","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fblog.rtc-lab.com%2Fentry%2F2024%2F05%2F23%2F125328\" title=\"Verilog \u306e\u6f14\u7b97\u6642\u306e\u5e45\u62e1\u5f35\u3067\u3057\u304f\u3058\u3063\u305f\u8a71 - Ryuz&#39;s tech blog\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","image_url":null}