{"provider_name":"Hatena Blog","width":"100%","provider_url":"https://hatena.blog","blog_title":"Ryuz's tech blog","height":"190","author_url":"https://blog.hatena.ne.jp/Ryuz88/","type":"rich","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fblog.rtc-lab.com%2Fentry%2F2024%2F05%2F23%2F172249\" title=\"Xilinx FPGA \u306e FF \u307e\u308f\u308a - Ryuz&#39;s tech blog\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","categories":["FPGA"],"published":"2024-05-23 17:22:49","description":"\u306f\u3058\u3081\u306b FPGA \u306f\u5404\u793e\u3057\u3070\u3057\u540c\u671f\u30ea\u30bb\u30c3\u30c8\u63a8\u5968\u3060\u3063\u305f\u3068\u8a18\u61b6\u3057\u3066\u3044\u307e\u3059\u304c\u3001FF\u5468\u306b\u306f\u3044\u308d\u3044\u308d\u6a5f\u80fd\u304c\u3064\u3044\u3066\u307e\u3059\u3002 KV260 (Zynq UltraScale+ MPSoC) \u7528\u306e\u5408\u6210\u7d50\u679c\u306e\u4e2d\u8eab\u3092\u8997\u3044\u3066\u307f\u305f\u306e\u3067\u30e1\u30e2\u3067\u3059\u3002 \u666e\u901a\u306b\u66f8\u3044\u3066\u307f\u308b \u79c1\u304c\u666e\u6bb5\u3088\u304f\u66f8\u304f\u66f8\u304d\u65b9\u304c\u4e0b\u8a18\u306e\u3088\u3046\u306a\u611f\u3058\u3067\u3059\u3002 module test( input var logic reset , input var logic clk , input var logic cke , input var logic din , output var logic dout ); always_ff @(posedge clk) begi\u2026","blog_url":"https://blog.rtc-lab.com/","image_url":"https://cdn-ak.f.st-hatena.com/images/fotolife/R/Ryuz88/20240523/20240523171912.png","author_name":"Ryuz88","url":"https://blog.rtc-lab.com/entry/2024/05/23/172249","version":"1.0","title":"Xilinx FPGA \u306e FF \u307e\u308f\u308a"}