{"url":"https://blog.rtc-lab.com/entry/2024/11/30/100019","author_url":"https://blog.hatena.ne.jp/Ryuz88/","categories":["FPGA","\u96d1\u8a18"],"height":"190","blog_url":"https://blog.rtc-lab.com/","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fblog.rtc-lab.com%2Fentry%2F2024%2F11%2F30%2F100019\" title=\"FPGA\u3092\u59cb\u3081\u308b\u3068\u304d\u306e\u58c1 - Ryuz&#39;s tech blog\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","published":"2024-11-30 10:00:19","blog_title":"Ryuz's tech blog","author_name":"Ryuz88","image_url":"https://m.media-amazon.com/images/I/51rJVeeRLvL._SL500_.jpg","provider_name":"Hatena Blog","width":"100%","title":"FPGA\u3092\u59cb\u3081\u308b\u3068\u304d\u306e\u58c1","version":"1.0","type":"rich","provider_url":"https://hatena.blog","description":"FPGA\u3092\u306f\u3058\u3081\u3066\u307f\u305f\u3044 \u300cFPGA\u3068\u3044\u3046\u4f55\u3084\u3089\u9762\u767d\u3044\u3082\u306e\u304c\u3042\u308b\u3089\u3057\u304f\u3066\u3001\u4f7f\u3046\u3068\u3059\u3054\u3044\u8a08\u7b97\u3084\u3044\u308d\u3044\u308d\u306a\u30c7\u30d0\u30a4\u30b9\u5236\u5fa1\u304c\u3067\u304d\u308b\u3089\u3057\u3044\u3002\u300d \u3068\u3001\u8208\u5473\u3092\u6301\u3063\u3066\u9802\u3051\u308b\u65b9\u306f\u305d\u308c\u306a\u308a\u306b\u3044\u3089\u3063\u3057\u3083\u308b\u306e\u3067\u306f\u306a\u3044\u3067\u3057\u3087\u3046\u304b\uff1f \u65e9\u901f\u306a\u3093\u3089\u304b\u306eHDL\u306a\u308b\u8a00\u8a9e\u3092\u52c9\u5f37\u3057\u3001\u4f8b\u3048\u3070 SystemVerilog \u3092\u5c11\u3057\u52c9\u5f37\u3059\u308c\u3070\u4e0b\u8a18\u306e\u3088\u3046\u306a\u30d7\u30ed\u30b0\u30e9\u30e0\u3092\u66f8\u304f\u3053\u3068\u304c\u51fa\u6765\u307e\u3059\u3002 \u5165\u529b\u30dd\u30fc\u30c8 a,b \u304b\u3089\u5165\u3063\u3066\u304f\u308b\u30c7\u30fc\u30bf\u3092\u30af\u30ed\u30c3\u30af\u30b5\u30a4\u30af\u30eb\u6bce\u306b\u52a0\u7b97\u3057\u3066c \u306b\u51fa\u529b\u3059\u308b\u30ed\u30b8\u30c3\u30af\u306e\u30bd\u30fc\u30b9\u3067\u3059\u3002 module add ( input logic reset, input logic clk, input logic [31:0] a, inpu\u2026"}