{"url":"https://cuscus.hatenadiary.jp/entry/2025/05/11/053447","blog_url":"https://cuscus.hatenadiary.jp/","title":"First draft of a report on the EDVAC\u3000\u548c\u8a33\u300012.0 \u30e1\u30e2\u30eaM\u306e\u5bb9\u91cf. \u4e00\u822c\u539f\u5247\u300012.1\uff5e12.3","type":"rich","width":"100%","author_name":"CUSCUS","provider_name":"Hatena Blog","version":"1.0","provider_url":"https://hatena.blog","height":"190","categories":[],"description":"\u76ee\u6b21\u3078 \u6b21\u3078 \u524d\u3078 12.0 CAPACITY OF THE MEMORY M. GENERAL PRINCIPLES 12.0 \u30e1\u30e2\u30eaM\u306e\u5bb9\u91cf\u3002\u4e00\u822c\u539f\u5247 12.1 We consider next the third specic part: the memory M. Memory devices were discussed in 7.5, 7.6, since they are needed as parts of the networks (cf. 7.4, 7.7 for , 8.3 for , 10.2 for ) and hence of CA itself (cf. the \u2026","published":"2025-05-11 05:34:47","author_url":"https://blog.hatena.ne.jp/CUSCUS/","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fcuscus.hatenadiary.jp%2Fentry%2F2025%2F05%2F11%2F053447\" title=\"First draft of a report on the EDVAC\u3000\u548c\u8a33\u300012.0 \u30e1\u30e2\u30eaM\u306e\u5bb9\u91cf. \u4e00\u822c\u539f\u5247\u300012.1\uff5e12.3 - \u30b5\u30a4\u30d0\u30cd\u30c6\u30a3\u30c3\u30af\u30b9\u3068\u306f\u4f55\u3060\u3063\u305f\u306e\u304b\uff1f\u3000\u4eca\u3001\u4f55\u3067\u3042\u308a\u5f97\u308b\u306e\u304b\uff1f\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","image_url":"https://cdn-ak.f.st-hatena.com/images/fotolife/C/CUSCUS/20250509/20250509194015.png","blog_title":"\u30b5\u30a4\u30d0\u30cd\u30c6\u30a3\u30c3\u30af\u30b9\u3068\u306f\u4f55\u3060\u3063\u305f\u306e\u304b\uff1f\u3000\u4eca\u3001\u4f55\u3067\u3042\u308a\u5f97\u308b\u306e\u304b\uff1f"}