{"image_url":"https://images-fe.ssl-images-amazon.com/images/I/41I%2B-J%2ByKIL._SL160_.jpg","published":"2017-12-16 01:00:00","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fe-tipsmemo.hatenablog.com%2Fentry%2F2017%2F12%2F16%2F010000\" title=\"Verilog \u30d3\u30c7\u30aa\u4fe1\u53f7\u51fa\u529b(Transition Minimized Differential Signaling) - e-tipsmemo\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","width":"100%","type":"rich","description":"\u3044\u308f\u3086\u308bHDMI\u306eV1.0\u3067DVI-D\u3068\u4e92\u63db\u306e\u30c7\u30fc\u30bf\u5f62\u5f0fe-tipsmemo.hatenablog.com \u306e\u7d9a\u304d\u3002 \u3068\u3044\u3063\u3066\u3082 e-tipsmemo.hatenablog.com \u3092Verilog\u306b\u3059\u308b\u3060\u3051 module encoding( input clk, input resetn, input [7:0] din, output [9:0] dout, input disp_area, input c0, input c1 ); function [3:0] ones(input [7:0] in); begin ones = {3'b0,in[7]}+{3'b0,in[6]}+{3\u2026","blog_title":"e-tipsmemo","categories":["\u7d44\u307f\u8fbc\u307f"],"height":"190","blog_url":"https://e-tipsmemo.hatenablog.com/","provider_url":"https://hatena.blog","provider_name":"Hatena Blog","author_url":"https://blog.hatena.ne.jp/katakanan/","version":"1.0","title":"Verilog \u30d3\u30c7\u30aa\u4fe1\u53f7\u51fa\u529b(Transition Minimized Differential Signaling)","url":"https://e-tipsmemo.hatenablog.com/entry/2017/12/16/010000","author_name":"katakanan"}