{"author_url":"https://blog.hatena.ne.jp/fullphong/","provider_url":"https://hatena.blog","title":"Xilinx\u306eUCF\u95a2\u9023\u8aad\u307f\u7269","categories":[],"blog_title":"\u53e4\u5ddd\u5236\u5fa1\u65e5\u8a18","author_name":"fullphong","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Ffullphong.hatenablog.com%2Fentry%2F2015%2F11%2F13%2F162036\" title=\"Xilinx\u306eUCF\u95a2\u9023\u8aad\u307f\u7269 - \u53e4\u5ddd\u5236\u5fa1\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","provider_name":"Hatena Blog","description":"\u96fb\u6c17\u56de\u8def/HDL/Xilinx ISE \u306b\u304a\u3051\u308b\u306e\u5236\u7d04\u306e\u4e0e\u3048\u65b9 - \u6b66\u5185\uff20\u7b51\u6ce2\u5927 FPGA\u306e\u90e8\u5c4b \u201dUCF\u306e\u66f8\u304d\u65b9\u201d\u306e\u76ee\u6b21","version":"1.0","image_url":"http://www.xilinx.com/itp/xilinx10/books/docs/timing_constraints_ug/timing_constraints_ug.pdf","type":"rich","published":"2015-11-13 16:20:36","width":"100%","height":"190","blog_url":"https://fullphong.hatenablog.com/","url":"https://fullphong.hatenablog.com/entry/2015/11/13/162036"}