{"author_name":"Hossy","description":"Altera MF \u3068\u306f\u3001Altera \u793e\u88fd\u306e CPLD, FPGA \u3067\u4f7f\u7528\u3067\u304d\u308b IP \u7fa4\u3067\u3059\u3002 \u5e73\u305f\u304f\u8a00\u3048\u3070 MegaWizard \u3067\u4f5c\u308c\u308b FIFO \u3084 SRAM \u306a\u3069\u306e\u3053\u3068\u3067\u3059\u3002 \uff08MegaWizard: Xilinx \u3067\u8a00\u3046 coregen \u306e\u3053\u3068\uff09 \u3053\u308c\u3092 QuartusII \u3067\u5408\u6210\u3059\u308b\u6642\u306f\u3044\u3044\u3093\u3067\u3059\u304c\u3001ModelSim \u3067\u30b7\u30df\u30e5\u30ec\u30fc\u30b7\u30e7\u30f3\u3059\u308b\u6642\u306b\u306f\u5c11\u3057\u3060\u3051\u30b3\u30c4\u304c\u8981\u308a\u307e\u3059\u3002 \u901a\u5e38\u3001\u30b7\u30df\u30e5\u30ec\u30fc\u30b7\u30e7\u30f3\u3059\u308b\u6642\u306f C:\\> vsim -quiet -do hoge.do work.tb_hoge\u306a\u3069\u3068\u3059\u308b\u308f\u3051\u3067\u3059\u304c\u3001\u3053\u3053\u3067 -L \u30aa\u30d7\u30b7\u30e7\u30f3\u3067 Altera MF \u306e\u30e9\u30a4\u30d6\u30e9\u30ea\u3092\u6307\u5b9a\u3057\u307e\u3059\u3002\u2026","blog_url":"https://hoshizuki.hateblo.jp/","categories":[],"provider_url":"https://hatena.blog","height":"190","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fhoshizuki.hateblo.jp%2Fentry%2F20101026%2Fp1\" title=\" Altera MF \u306e\u4f7f\u3044\u65b9 - \u307b\u3063\u3057\u30fc\u306e\u6280\u8853\u30cd\u30bf\u5099\u5fd8\u9332\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","author_url":"https://blog.hatena.ne.jp/Hossy/","type":"rich","image_url":null,"published":"2010-10-26 00:00:00","provider_name":"Hatena Blog","url":"https://hoshizuki.hateblo.jp/entry/20101026/p1","blog_title":"\u307b\u3063\u3057\u30fc\u306e\u6280\u8853\u30cd\u30bf\u5099\u5fd8\u9332","width":"100%","title":" Altera MF \u306e\u4f7f\u3044\u65b9","version":"1.0"}