{"published":"2015-10-18 16:39:23","author_url":"https://blog.hatena.ne.jp/KirIn/","url":"https://kirin.hatenadiary.jp/entry/2015/10/18/163923","provider_url":"https://hatena.blog","image_url":"http://ecx.images-amazon.com/images/I/51FPBmIDsSL.jpg","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fkirin.hatenadiary.jp%2Fentry%2F2015%2F10%2F18%2F163923\" title=\"Verilog HDL &amp; VHDL\u30c6\u30b9\u30c8\u30d9\u30f3\u30c1\u8a18\u8ff0\u306e\u521d\u6b69\u3000\u81ea\u5206\u7528\u30e1\u30e2 - KirIn \u843d\u66f8\u304d\u5e33\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","width":"100%","provider_name":"Hatena Blog","blog_url":"https://kirin.hatenadiary.jp/","height":"190","description":"Verilog HDL&VHDL\u30c6\u30b9\u30c8\u30d9\u30f3\u30c1\u8a18\u8ff0\u306e\u521d\u6b69 (DESIGN WAVE MOOK)\u4f5c\u8005: \u5b89\u5ca1\u8cb4\u5fd7\u51fa\u7248\u793e/\u30e1\u30fc\u30ab\u30fc: CQ\u51fa\u7248\u767a\u58f2\u65e5: 2011/03/30\u30e1\u30c7\u30a3\u30a2: \u5358\u884c\u672c\u8cfc\u5165: 1\u4eba \u30af\u30ea\u30c3\u30af: 3\u56de\u3053\u306e\u5546\u54c1\u3092\u542b\u3080\u30d6\u30ed\u30b0 (1\u4ef6) \u3092\u898b\u308b Verilog\u306e\u30c6\u30b9\u30c8\u30d9\u30f3\u30c1\u8a18\u8ff0\u306b\u3064\u3044\u3066\u8a00\u53ca\u3057\u3066\u3044\u308b\u65e5\u672c\u8a9e\u306e\u672c\u306f\u3042\u307e\u308a\u306a\u3044\u3068\u601d\u3044\u307e\u3059\u3002 \u3044\u3044\u672c\u3067\u3059\u3002 \u4ee5\u4e0b\u306f\u81ea\u5206\u7528\u30e1\u30e2\u3067\u3059\u3002","version":"1.0","title":"Verilog HDL & VHDL\u30c6\u30b9\u30c8\u30d9\u30f3\u30c1\u8a18\u8ff0\u306e\u521d\u6b69\u3000\u81ea\u5206\u7528\u30e1\u30e2","blog_title":"KirIn \u843d\u66f8\u304d\u5e33","author_name":"KirIn","categories":["verilogHDL"],"type":"rich"}