{"categories":["Vivado HLS","FPGA"],"blog_title":"KirIn \u843d\u66f8\u304d\u5e33","version":"1.0","published":"2016-01-18 01:45:12","title":"Vivado HLS \u52c9\u5f37\u3000\u305d\u306e0","author_name":"KirIn","url":"https://kirin.hatenadiary.jp/entry/2016/01/18/014512","provider_url":"https://hatena.blog","type":"rich","height":"190","image_url":"http://cdn-ak.f.st-hatena.com/images/fotolife/K/KirIn/20160118/20160118012751.png","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fkirin.hatenadiary.jp%2Fentry%2F2016%2F01%2F18%2F014512\" title=\"Vivado HLS \u52c9\u5f37\u3000\u305d\u306e0 - KirIn \u843d\u66f8\u304d\u5e33\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","description":"\u305d\u308d\u305d\u308d\u9ad8\u4f4d\u5408\u6210\u306b\u3082\u624b\u3092\u51fa\u3055\u306a\u3051\u308c\u3070\u3068\u3044\u3046\u3053\u3068\u3067\u3001\u305d\u306e\u6e96\u5099 \u3068\u308a\u3042\u3048\u305a\u30c1\u30e5\u30fc\u30c8\u30ea\u30a2\u30eb\u3067\u624b\u3092\u52d5\u304b\u3057\u307e\u3059\u3002 \u53c2\u8003\u8cc7\u6599 Vivado Design Suite \u30e6\u30fc\u30b6\u30fc \u30ac\u30a4\u30c9 \u9ad8\u4f4d\u5408\u6210 Vivado Design Suite Tutorial High-Level Synthesis UG871 (v 2014.1) May 6, 2014 \u30bd\u30fc\u30b9\u30b3\u30fc\u30c9\u305f\u3061 Create New Project \u30c0\u30a6\u30f3\u30ed\u30fc\u30c9\u3057\u305f\u30d5\u30a9\u30eb\u30c0\u306eug871-design-files\\Vivado_HLS_Tutorial\\Introduction\\lab1\u306b\u30bd\u30fc\u30b9\u30b3\u30fc\u30c9\u304c\u5165\u3063\u3066\u3044\u308b\u3002 Create New Project\u2026","author_url":"https://blog.hatena.ne.jp/KirIn/","blog_url":"https://kirin.hatenadiary.jp/","provider_name":"Hatena Blog","width":"100%"}