{"version":"1.0","width":"100%","type":"rich","height":"190","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fkiririmode.hatenablog.jp%2Fentry%2F20080504%2Fp3\" title=\"\u554f\u984c3-29 (3.3.4 A Simulator for Digital Circuits) - \u7406\u7cfb\u5b66\u751f\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","description":"or-gate \u3092\uff0cand-gate \u3068 inverter \u3067\u69cb\u6210\u3057\u308d\u3068\u3044\u3046\u554f\u984c\uff0e \u3053\u3093\u306a\u611f\u3058\u304b\u3068\u601d\u308f\u308c\uff0e (define (or-gate a1 a2 output) (let ((x (make-wire)) (y (make-wire)) (z (make-wire))) (inverter a1 x) (inverter a2 y) (and-gate x y z) (inverter z output)) 'ok) \u9045\u5ef6\u306e\u65b9\u306f\uff0cinverter 2 \u3064\u5206\u3068 and-gate 1 \u3064\u5206\u3068\u3044\u3046\u3053\u3068\u3067\uff0c2*inverter-delay + and-gate-delay \u306b\u306a\u308b\u304b\u306a\u30fc\uff0e","title":"\u554f\u984c3-29 (3.3.4 A Simulator for Digital Circuits)","author_name":"kiririmode","provider_url":"https://hatena.blog","author_url":"https://blog.hatena.ne.jp/kiririmode/","url":"https://kiririmode.hatenablog.jp/entry/20080504/p3","blog_url":"https://kiririmode.hatenablog.jp/","image_url":null,"provider_name":"Hatena Blog","blog_title":"\u7406\u7cfb\u5b66\u751f\u65e5\u8a18","categories":["SICP"],"published":"2008-05-04 00:00:02"}