{"description":"VerilogHDL\u3067\u66f8\u304d\u59cb\u3081\u306e\u30c6\u30f3\u30d7\u30ec\u30fc\u30c8eclipse\u306eveditor(http://sourceforge.net/projects/veditor/)\u3092\u5165\u308c\u3066 Window>Preferences>Verilog/VHDL Editor>Templates\u3067\u88dc\u5b8c\u5019\u88dc\u306b\u767b\u9332\u3057\u3066\u304a\u304f\u3068\u5e78\u305b\u306b\u306a\u308c\u308b\u3002 /* * module: ${name} * Date:${date} * Author: ${user} * Description * ${cursor} */ /* * Copyright (C) 2013 Keisuke SUZUKI * Licensed under the Apac\u2026","blog_url":"https://ksksue.hatenadiary.org/","categories":["FPGA","VerilogHDL"],"provider_name":"Hatena Blog","version":"1.0","author_url":"https://blog.hatena.ne.jp/ksksue/","author_name":"ksksue","provider_url":"https://hatena.blog","image_url":null,"html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fksksue.hatenadiary.org%2Fentry%2F20130421%2F1366570750\" title=\" VerilogHDL\u30c6\u30f3\u30d7\u30ec\u30fc\u30c8 - GeekleBoard\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","type":"rich","width":"100%","blog_title":"GeekleBoard","url":"https://ksksue.hatenadiary.org/entry/20130421/1366570750","published":"2013-04-21 03:59:10","title":" VerilogHDL\u30c6\u30f3\u30d7\u30ec\u30fc\u30c8","height":"190"}