{"width":"100%","url":"https://lansen.hatenadiary.org/entry/20100502/1272823065","author_url":"https://blog.hatena.ne.jp/Lansen/","image_url":null,"description":"\u3061\u3087\u3063\u3068\u9593\u304c\u958b\u3044\u3066\u3057\u307e\u3044\u307e\u3057\u305f\u304c\u3001\u7d9a\u304d\u3067\u3059\u3002 NAND\u30d5\u30e9\u30c3\u30b7\u30e5\u306b\u306f\u3069\u306e\u304f\u3089\u3044\u30d3\u30c3\u30c8\u30a8\u30e9\u30fc\u304c\u767a\u751f\u3059\u308b\u304b\uff1f \u5b9f\u969b\u306eNAND\u30d5\u30e9\u30c3\u30b7\u30e5\u306e\u30d3\u30c3\u30c8\u30a8\u30e9\u30fc\u306e\u767a\u751f\u7387\u306b\u3064\u3044\u3066\u3001\u4ee5\u4e0b\u306e\u6587\u732e\u304c\u8208\u5473\u6df1\u3044\u306e\u3067\u7d39\u4ecb\u3057\u3066\u307f\u305f\u3044\u3068\u601d\u3044\u307e\u3059\u3002 N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares, F. Trivedi, E. Goodness, and L. R. Nevill. \"Bit Error Rate in NAND Flash Memories,\" In Proc. of IEEE International Reliabilit\u2026","version":"1.0","type":"rich","blog_url":"https://lansen.hatenadiary.org/","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Flansen.hatenadiary.org%2Fentry%2F20100502%2F1272823065\" title=\"(2) - Lansen\u306e\u73fe\u5b9f\u9003\u907f\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","blog_title":"Lansen\u306e\u73fe\u5b9f\u9003\u907f\u65e5\u8a18","height":"190","provider_name":"Hatena Blog","categories":["SSD\u306e\"\u5bff\u547d\"\u3092\u7406\u89e3\u3059\u308b"],"author_name":"Lansen","title":"(2)","provider_url":"https://hatena.blog","published":"2010-05-02 02:57:45"}