{"image_url":null,"blog_url":"https://minettyo.hatenablog.com/","provider_name":"Hatena Blog","width":"100%","author_url":"https://blog.hatena.ne.jp/minettyo/","provider_url":"https://hatena.blog","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fminettyo.hatenablog.com%2Fentry%2Fcontents_logicdesign\" title=\"\u8ad6\u7406\u56de\u8def\u8a2d\u8a08\u306e\u76ee\u6b21\uff1a - \u307f\u306d\u3063\u3061\u3087\u306e\u30de\u30a4\u30b3\u30f3\u95a2\u4fc2\u30d6\u30ed\u30b0\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","description":"\u6700\u7d42\u66f4\u65b0\uff1a2023-04-11 \u521d\u51fa\u63b2\u8f09\uff1a2021-01-20 \u30b7\u30df\u30e5\u30ec\u30fc\u30bf\uff1a Windows \u3067\u3082\u52d5\u304f\u3001\u7121\u511f\u306e Verilog HDL \u30b7\u30df\u30e5\u30ec\u30fc\u30bf\u30fc\u3001Icarus Verilog WSL \u3067 \u7121\u511f\u306e Verilog \u306a \u30b5\u30a4\u30af\u30eb\u30d9\u30fc\u30b9\u30b7\u30df\u30e5\u30ec\u30fc\u30bf Verilator \u3092\u4f7f\u3046 \u7121\u511f\u306a Verilog \u30b7\u30df\u30e5\u30ec\u30fc\u30bf Verilator \u306e\u30c6\u30b9\u30c8\u30d9\u30f3\u30c1\u3092 SystemC \u3067\u4f5c\u308b WSL \u306e Verilator \u3067 \u30c8\u30ec\u30fc\u30b9\u6ce2\u5f62\u3092\u30c0\u30f3\u30d7\u3059\u308b Verilog HDL \u30b3\u30fc\u30c7\u30a3\u30f3\u30b0\uff1a \u52b9\u7387\u7684\u306a Verilog HDL \u306e\u30b3\u30fc\u30c7\u30a3\u30f3\u30b0\u624b\u6cd5 CPU \u30b3\u30a2\u306e\u30b7\u30df\u30e5\u30ec\u30fc\u30b7\u30e7\u30f3\uff1a ARM Cortex-M0 \u30b3\u2026","url":"https://minettyo.hatenablog.com/entry/contents_logicdesign","author_name":"minettyo","categories":["Contents"],"published":"2021-01-20 01:56:22","height":"190","version":"1.0","blog_title":"\u307f\u306d\u3063\u3061\u3087\u306e\u30de\u30a4\u30b3\u30f3\u95a2\u4fc2\u30d6\u30ed\u30b0","type":"rich","title":"\u8ad6\u7406\u56de\u8def\u8a2d\u8a08\u306e\u76ee\u6b21\uff1a"}