{"type":"rich","title":"\u30ec\u30b8\u30b9\u30bf\u81ea\u52d5\u751f\u6210","version":"1.0","blog_url":"https://morning-pumpkin.hatenablog.com/","categories":["systemverilog","verilog","VHDL","FPGA"],"height":"190","width":"100%","author_name":"morning-pumpkin","provider_url":"https://hatena.blog","provider_name":"Hatena Blog","image_url":null,"html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmorning-pumpkin.hatenablog.com%2Fentry%2F2021%2F12%2F19%2F111847\" title=\"\u30ec\u30b8\u30b9\u30bf\u81ea\u52d5\u751f\u6210 - morning-pumpkin\u2019s blog\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","description":"\u5236\u5fa1\u30ec\u30b8\u30b9\u30bf (CSR) \u3092\u81ea\u52d5\u751f\u6210\u3059\u308b - Qiita","url":"https://morning-pumpkin.hatenablog.com/entry/2021/12/19/111847","published":"2021-12-19 11:18:47","author_url":"https://blog.hatena.ne.jp/morning-pumpkin/","blog_title":"morning-pumpkin\u2019s blog"}