{"author_url":"https://blog.hatena.ne.jp/morning-pumpkin/","height":"190","image_url":null,"author_name":"morning-pumpkin","blog_title":"morning-pumpkin\u2019s blog","type":"rich","published":"2021-12-22 14:03:16","width":"100%","description":"\u96fb\u5b50\u56de\u8def\u65e5\u548c - Interface(1) \u30c7\u30b6\u30a4\u30f3\u5411\u3051\uff08\u8ad6\u7406\u5408\u6210\u53ef\u80fd\uff09SystemVerilog\u8a18\u8ff0 - Qiita SystemVerilog\u3067\u904a\u307c\u3046\uff01 All-of-SystemVerilog/Models.md at main \u00b7 vengineer-systemverilog/All-of-SystemVerilog \u00b7 GitHub","blog_url":"https://morning-pumpkin.hatenablog.com/","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmorning-pumpkin.hatenablog.com%2Fentry%2F2021%2F12%2F22%2F140316\" title=\"systemverilog\u53c2\u8003\u8a18\u4e8b - morning-pumpkin\u2019s blog\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","provider_url":"https://hatena.blog","url":"https://morning-pumpkin.hatenablog.com/entry/2021/12/22/140316","version":"1.0","categories":[],"provider_name":"Hatena Blog","title":"systemverilog\u53c2\u8003\u8a18\u4e8b"}