{"width":"100%","blog_title":"FPGA\u958b\u767a\u65e5\u8a18","url":"https://msyksphinz.hatenablog.com/entry/2015/04/11/041031","provider_name":"Hatena Blog","title":"Verilog-Perl \u306e vhier \u3092\u4f7f\u3063\u3066\u30e2\u30b8\u30e5\u30fc\u30eb\u69cb\u6210\u3092\u628a\u63e1\u3059\u308b","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmsyksphinz.hatenablog.com%2Fentry%2F2015%2F04%2F11%2F041031\" title=\"Verilog-Perl \u306e vhier \u3092\u4f7f\u3063\u3066\u30e2\u30b8\u30e5\u30fc\u30eb\u69cb\u6210\u3092\u628a\u63e1\u3059\u308b - FPGA\u958b\u767a\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","image_url":null,"provider_url":"https://hatena.blog","author_name":"msyksphinz","description":"Verilog-Perl \u306b\u306f\u3001 vhier \u3068\u3044\u3046\u30e2\u30b8\u30e5\u30fc\u30eb\u968e\u5c64\u3092\u8a8d\u8b58\u3059\u308b\u30b9\u30af\u30ea\u30d7\u30c8\u304c\u3042\u308b\u3002 \u3053\u308c\u3092\u4f7f\u3063\u3066\u73fe\u5728\u958b\u767a\u3057\u3066\u3044\u308b\u30e2\u30b8\u30e5\u30fc\u30eb\u306e\u968e\u5c64\u3092\u628a\u63e1\u3057\u3066\u307f\u3088\u3046\u3002 Manual-verilog-perl - Verilog-Perl - Veripoolwww.veripool.org vhier -f dotf/pulsar1_top.f --top-module pulsar1_top -o pulsar1.hier --cells --forest --instance \u3068\u3059\u308b\u3068\u3001pulsar1.hier \u306b\u73fe\u5728\u306eVerilog\u30e2\u30b8\u30e5\u30fc\u30eb\u306e\u968e\u5c64\u69cb\u6210\u304c\u8868\u793a\u3055\u308c\u308b\u3002\u5165\u529b\u306fdotf/pulsar1\u2026","published":"2015-04-11 04:10:31","author_url":"https://blog.hatena.ne.jp/msyksphinz/","height":"190","categories":[],"type":"rich","blog_url":"https://msyksphinz.hatenablog.com/","version":"1.0"}