{"author_url":"https://blog.hatena.ne.jp/msyksphinz/","width":"100%","description":"\u524d\u56de\u307e\u3067\u3067\u3001\u3069\u3046\u306b\u304b\u3053\u3046\u306b\u304bCMake\u3067Vivado Simulator\u306e\u30d3\u30eb\u30c9\u74b0\u5883\u3092\u69cb\u7bc9\u3057\u305f\u3002 \u3053\u3053\u307e\u3067\u51fa\u6765\u305f\u3089\u3001\u5b9f\u306fCTest\u306b\u3088\u308b\u30c6\u30b9\u30c8\u306e\u8ffd\u52a0\u306f\u5bb9\u6613\u306a\u306e\u3060\u3002 CMakeLists.txt\u306b\u4ee5\u4e0b\u3092\u8ffd\u52a0\u3057\u3066\u307f\u305f\u3002 # CTest enable_testing() add_test (NAME basic_test COMMAND /cygdrive/c/Xilinx/Vivado/2015.4/bin/xsim --R top_sim) \u4eca\u56de\u306fxsim\u306e\u30b3\u30de\u30f3\u30c9\u3092\u8ffd\u52a0\u3057\u3001\u30aa\u30d7\u30b7\u30e7\u30f3\u7121\u3057\u3060\u304c\u3001\u5f15\u6570\u3068\u3057\u3066\u8ffd\u52a0\u3059\u308b\u304b\u3001\u5916\u90e8\u304b\u3089\u5236\u5fa1\u30d5\u30a1\u30a4\u30eb\u3092\u4e0e\u3048\u308b\u3053\u3068\u3067\u8907\u6570\u306e\u30c6\u30b9\u30c8\u3082\u8ffd\u52a0\u3067\u304d\u308b\u3060\u308d\u3046\u3002 \u3055\u3089\u306b\u8a00\u3046\u306a\u2026","url":"https://msyksphinz.hatenablog.com/entry/2016/01/09/020000","type":"rich","provider_url":"https://hatena.blog","version":"1.0","blog_url":"https://msyksphinz.hatenablog.com/","title":"CMake\u306b\u3088\u308aVerilog\u306e\u30d3\u30eb\u30c9\u3092\u7ba1\u7406\u3059\u308b\u305f\u3081\u306e\u8abf\u67fb(2. CTest\u306b\u3088\u308b\u30c6\u30b9\u30c8\u8ffd\u52a0)","blog_title":"FPGA\u958b\u767a\u65e5\u8a18","height":"190","image_url":null,"provider_name":"Hatena Blog","published":"2016-01-09 02:00:00","author_name":"msyksphinz","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmsyksphinz.hatenablog.com%2Fentry%2F2016%2F01%2F09%2F020000\" title=\"CMake\u306b\u3088\u308aVerilog\u306e\u30d3\u30eb\u30c9\u3092\u7ba1\u7406\u3059\u308b\u305f\u3081\u306e\u8abf\u67fb(2. CTest\u306b\u3088\u308b\u30c6\u30b9\u30c8\u8ffd\u52a0) - FPGA\u958b\u767a\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","categories":["Verilog"]}