{"author_name":"msyksphinz","blog_url":"https://msyksphinz.hatenablog.com/","width":"100%","url":"https://msyksphinz.hatenablog.com/entry/2017/10/08/020000","height":"190","blog_title":"FPGA\u958b\u767a\u65e5\u8a18","type":"rich","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmsyksphinz.hatenablog.com%2Fentry%2F2017%2F10%2F08%2F020000\" title=\"VHDL/Verilog\u306e\u30c6\u30b9\u30c6\u30a3\u30f3\u30b0\u30d5\u30ec\u30fc\u30e0\u30ef\u30fc\u30afVUnit\u3092\u8a66\u884c\u3059\u308b - FPGA\u958b\u767a\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","author_url":"https://blog.hatena.ne.jp/msyksphinz/","description":"VUnit \u306f VHDL/SystemVerilog\u306e\u30c6\u30b9\u30c6\u30a3\u30f3\u30b0\u30d5\u30ec\u30fc\u30e0\u30ef\u30fc\u30af\u3060\u3002VUnit\u306b\u306f\u3044\u304f\u3064\u304b\u30c6\u30b9\u30c8\u30d1\u30bf\u30f3\u304c\u7528\u610f\u3055\u308c\u3066\u3044\u308b\u304c\u3001\u5c11\u3057\u81ea\u5206\u3067\u3082\u30c6\u30b9\u30c8\u30d1\u30bf\u30f3\u3092\u7528\u610f\u3057\u3066\u307f\u3088\u3046\u3002 \u4f5c\u3063\u3066\u307f\u305f\u306e\u306f\u300132bit\u00d732bit=64bit\u306e\u7b26\u53f7\u306a\u3057\u6574\u6570\u306e\u6f14\u7b97\u5668\u3092\u5b9f\u88c5\u3057\u3066\u3001VUnit\u3067\u30c6\u30b9\u30c8\u3092\u5b9f\u884c\u3057\u3066\u307f\u3088\u3046\u3002\u3053\u306e\u6f14\u7b97\u5668\u306f4\u30b5\u30a4\u30af\u30eb\u306732bit\u00d732bit=64bit\u306e\u6f14\u7b97\u3092\u5b9f\u884c\u3059\u308b\u3002 VUnit\u306e\u30c6\u30b9\u30c8\u30b9\u30a4\u30fc\u30c8\u306e\u5b9f\u88c5 VUnit\u306e\u30c6\u30b9\u30c8\u30b9\u30a4\u30fc\u30c8\u3092\u5b9f\u88c5\u3057\u3066\u307f\u308b\u3002\u57fa\u672c\u7684\u306b\u3001TEST_CASE\u306b\u30c6\u30b9\u30c8\u3092\u5b9a\u7fa9\u3057\u3066\u3001\u30c6\u30b9\u30c8\u5185\u5bb9\u3092\u8a18\u8ff0\u3057\u3066\u3044\u308b\u3002 \u4eca\u56de\u306f\u3001\u4ee5\u4e0b\u306e\u30c6\u30b9\u30c8\u3092\u8a18\u8ff0\u3057\u305f\u3002 test_0 : test_1 :\u2026","title":"VHDL/Verilog\u306e\u30c6\u30b9\u30c6\u30a3\u30f3\u30b0\u30d5\u30ec\u30fc\u30e0\u30ef\u30fc\u30afVUnit\u3092\u8a66\u884c\u3059\u308b","published":"2017-10-08 02:00:00","version":"1.0","image_url":"https://cdn-ak.f.st-hatena.com/images/fotolife/m/msyksphinz/20171009/20171009005946.png","provider_name":"Hatena Blog","categories":[],"provider_url":"https://hatena.blog"}