{"version":"1.0","categories":["RISC-V"],"description":"RISC-V 7th Workshop\u3067\u306f\u3001Vector Extension\u306e\u8aac\u660e\u304c\u306a\u3055\u308c\u3066\u3044\u308b\u3002 The RISC-V Vector ISA https://content.riscv.org/wp-content/uploads/2017/12/Wed-1330-RISCVRogerEspasaVEXT-v4.pdf \u8cc7\u6599\u3092\u8aad\u307f\u306a\u304c\u3089\u307e\u3068\u3081\u3066\u307f\u308b\u3002\u8ffd\u8a18\u306e\u53ef\u80fd\u6027\u3042\u308a\u3002 RISC-V Vector Extension\u306e\u7279\u5fb4\u3068\u3057\u3066\u306f\u3001 \u306a\u308b\u3079\u304f\u30b3\u30f3\u30d1\u30af\u30c8\u306b\u3059\u308b\u3053\u3068\u3002 \u30d9\u30af\u30c8\u30eb\u30ec\u30b8\u30b9\u30bf\u306e\u51e6\u7406\u306b\u30de\u30b9\u30af\u3092\u52a0\u3048\u3001\u4efb\u610f\u306e\u8981\u7d20\u306e\u307f\u6f14\u7b97\u304c\u9069\u7528\u3055\u308c\u308b\u3088\u3046\u306b\u3059\u308b\u3002 \u30b9\u30ab\u30e9\u30fc\u3001\u30d9\u30af\u30c8\u30eb\u3001\u884c\u5217\u306e\u5f62\u5f0f\u306a\u3069\u3092\u30b5\u30dd\u30fc\u30c8\u3059\u308b\u2026","provider_url":"https://hatena.blog","url":"https://msyksphinz.hatenablog.com/entry/2017/12/22/020000","width":"100%","blog_title":"FPGA\u958b\u767a\u65e5\u8a18","author_url":"https://blog.hatena.ne.jp/msyksphinz/","published":"2017-12-22 02:00:00","author_name":"msyksphinz","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmsyksphinz.hatenablog.com%2Fentry%2F2017%2F12%2F22%2F020000\" title=\"7th RISC-V Workshop \u306e Vector Extension Proposal \u6982\u8981 - FPGA\u958b\u767a\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","type":"rich","blog_url":"https://msyksphinz.hatenablog.com/","provider_name":"Hatena Blog","height":"190","image_url":"https://cdn-ak.f.st-hatena.com/images/fotolife/m/msyksphinz/20171222/20171222012123.png","title":"7th RISC-V Workshop \u306e Vector Extension Proposal \u6982\u8981"}