{"height":"190","title":"SiFive Webinar \"Part III: Evaluating SiFive RISC-V Core IP\" \u8cc7\u6599","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmsyksphinz.hatenablog.com%2Fentry%2F2018%2F01%2F29%2F040000\" title=\"SiFive Webinar &quot;Part III: Evaluating SiFive RISC-V Core IP&quot; \u8cc7\u6599 - FPGA\u958b\u767a\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","description":"\u95a2\u9023\u8a18\u4e8b SiFive Webinar \"Part II: Introduction to SiFive RISC-V Core\" \u8074\u8b1b \"An Introduction to RISC-V Architecture for Embedded Developers\" \u8074\u8b1b SiFive\u306eWebinar\u304c\u66f4\u65b0\u3055\u308c\u3066\u3044\u305f\u3002 \u30b9\u30b1\u30b8\u30e5\u30fc\u30eb\u306f\u77e5\u3063\u3066\u3044\u305f\u306e\u3060\u3051\u308c\u3069\u3001\u771f\u591c\u4e2d\u306f\u9045\u3059\u304e\u308b\u3002\u3002\u3002 \u3061\u3087\u3063\u3068\u53d7\u8b1b\u4e0d\u80fd\u3002\u3002\u3002 Webinar Catalogue Webinar Catalogue via kwout \u5185\u5bb9\u3068\u3057\u3066\u306f\u3001\u6709\u6599\u306eIP\u30b3\u30a2\u3092\u8a55\u4fa1\u3059\u308b\u624b\u6cd5\u304c\u30e1\u30a4\u30f3\u3060\u3002 E31\u3068E51\u306eVerilog\u3092\u30c0\u30a6\u30f3\u30ed\u30fc\u30c9\u3057\u2026","image_url":"http://kwout.com/cutout/7/6e/r9/4x5.jpg","url":"https://msyksphinz.hatenablog.com/entry/2018/01/29/040000","width":"100%","provider_name":"Hatena Blog","author_url":"https://blog.hatena.ne.jp/msyksphinz/","type":"rich","version":"1.0","categories":["RISC-V"],"published":"2018-01-29 04:00:00","blog_url":"https://msyksphinz.hatenablog.com/","author_name":"msyksphinz","blog_title":"FPGA\u958b\u767a\u65e5\u8a18","provider_url":"https://hatena.blog"}