{"author_name":"msyksphinz","provider_url":"https://hatena.blog","title":"Chisel2\u3068Chisel3\u3067\u306eVerilog/C++\u30b3\u30fc\u30c9\u751f\u6210\u30d5\u30ed\u30fc\u306e\u9055\u3044","image_url":"https://cdn-ak.f.st-hatena.com/images/fotolife/m/msyksphinz/20181105/20181105012126.png","version":"1.0","blog_title":"FPGA\u958b\u767a\u65e5\u8a18","description":"Chisel\u306b\u306f\u30d0\u30fc\u30b8\u30e7\u30f3\u304c\u3042\u308a\u3001Chisel2\u3068Chisel3\u304c\u516c\u958b\u3055\u308c\u3066\u3044\u308b\u3002 \u5fae\u5999\u306b\u6587\u6cd5\u304c\u7570\u306a\u3063\u3066\u3044\u308b\u306e\u3067\u8981\u6ce8\u610f\u3060\u3002 Chisel2\u3067\u306fVerilog\u3068C++\u3092\u751f\u6210\u3059\u308b\u65b9\u6cd5\u304c\u516c\u958b\u3055\u308c\u3066\u3044\u308b\u304c\u3001Chisel3\u3067\u306f\u3069\u3046\u3060\u308d\u3046\u3002 Chisel2\u3067\u306eVerilog\u3068C++\u306e\u751f\u6210\u65b9\u6cd5\u306b\u3064\u3044\u3066\u306f\u3001\u4ee5\u4e0b\u306e\u30b5\u30a4\u30c8\u306b\u307e\u3068\u3081\u3089\u308c\u3066\u3044\u308b\u3002 \u3068\u601d\u3063\u3066\u3044\u308d\u3044\u308d\u63a2\u3057\u305f\u3089\u81ea\u5206\u306e\u30d6\u30ed\u30b0\u3060\u3063\u305f\u3002 github.com msyksphinz.hatenablog.com src/main/scala/hello/Hello.scala package Hello import Chisel._ class Hello ex\u2026","categories":["RISC-V","FIRRTL","Chisel"],"height":"190","published":"2018-11-08 04:00:00","width":"100%","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmsyksphinz.hatenablog.com%2Fentry%2F2018%2F11%2F08%2F040000\" title=\"Chisel2\u3068Chisel3\u3067\u306eVerilog/C++\u30b3\u30fc\u30c9\u751f\u6210\u30d5\u30ed\u30fc\u306e\u9055\u3044 - FPGA\u958b\u767a\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","blog_url":"https://msyksphinz.hatenablog.com/","author_url":"https://blog.hatena.ne.jp/msyksphinz/","type":"rich","provider_name":"Hatena Blog","url":"https://msyksphinz.hatenablog.com/entry/2018/11/08/040000"}