{"provider_url":"https://hatena.blog","blog_url":"https://msyksphinz.hatenablog.com/","author_url":"https://blog.hatena.ne.jp/msyksphinz/","type":"rich","blog_title":"FPGA\u958b\u767a\u65e5\u8a18","provider_name":"Hatena Blog","width":"100%","categories":[],"height":"190","image_url":null,"url":"https://msyksphinz.hatenablog.com/entry/2022/05/30/040000","title":"clang\u3067RISC-V Vector Extension\u306eAuto Vectorization\u3092\u8a66\u3059","author_name":"msyksphinz","version":"1.0","description":"Ubuntu 22.04 LTS\u4e0a\u3067\u30a4\u30f3\u30b9\u30c8\u30fc\u30eb\u3067\u304d\u308bclang14\u3092\u8a66\u3059\u3002 void vector_test (const long long *a, const long long *b, long long *c) { for (int i = 0; i < 256; i++) { c[i] = a[i] + b[i]; } return; } clang-14 -c vector_test.c -menable-experimental-extensions -march=rv64gcv -target riscv64 -O3 -mllvm --riscv-v-vector-bits-\u2026","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmsyksphinz.hatenablog.com%2Fentry%2F2022%2F05%2F30%2F040000\" title=\"clang\u3067RISC-V Vector Extension\u306eAuto Vectorization\u3092\u8a66\u3059 - FPGA\u958b\u767a\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","published":"2022-05-30 04:00:00"}