{"type":"rich","blog_title":"FPGA\u958b\u767a\u65e5\u8a18","url":"https://msyksphinz.hatenablog.com/entry/2022/10/19/040000","provider_name":"Hatena Blog","author_name":"msyksphinz","image_url":null,"version":"1.0","categories":[],"description":"RISC-V Vector Intrinsic\u306e\u30c9\u30ad\u30e5\u30e1\u30f3\u30c8\u3067\u306f\u3001\u30b5\u30f3\u30d7\u30eb\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u304c\u3044\u304f\u3064\u304b\u683c\u7d0d\u3055\u308c\u3066\u3044\u308b\u3002 https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/examples \u305d\u308c\u305e\u308c\u306e\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u306b\u304a\u3044\u3066\u3001\u3069\u306e\u3088\u3046\u306b\u30d9\u30af\u30c8\u30eb\u547d\u4ee4\u304c\u4f7f\u7528\u3055\u308c\u3066\u3044\u308b\u306e\u304b\u3092\u898b\u3066\u307f\u308b\u3053\u3068\u306b\u3057\u305f\u3002 rvv_strcpy char *strcpy_vec(char *dst, const char *src) { char *save = dst; size_t vlmax = vsetvlmax_e8m8(); long firs\u2026","provider_url":"https://hatena.blog","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmsyksphinz.hatenablog.com%2Fentry%2F2022%2F10%2F19%2F040000\" title=\"RISC-V Vector intrinsic\u306e\u30b5\u30f3\u30d7\u30eb\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u3092\u89e3\u6790\u3059\u308b - FPGA\u958b\u767a\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","height":"190","width":"100%","title":"RISC-V Vector intrinsic\u306e\u30b5\u30f3\u30d7\u30eb\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u3092\u89e3\u6790\u3059\u308b","author_url":"https://blog.hatena.ne.jp/msyksphinz/","published":"2022-10-19 04:00:00","blog_url":"https://msyksphinz.hatenablog.com/"}