{"author_name":"msyksphinz","author_url":"https://blog.hatena.ne.jp/msyksphinz/","width":"100%","categories":[],"title":"RISC-V Vector 1.0 \u3092\u30b5\u30dd\u30fc\u30c8\u3059\u308b\u30aa\u30fc\u30d7\u30f3\u30bd\u30fc\u30b9CPU Ara\u3092\u8a66\u3059 (2. \u6ce2\u5f62\u306e\u53d6\u5f97\u65b9\u6cd5)","image_url":"https://cdn-ak.f.st-hatena.com/images/fotolife/m/msyksphinz/20230509/20230509141347.png","blog_url":"https://msyksphinz.hatenablog.com/","provider_url":"https://hatena.blog","provider_name":"Hatena Blog","height":"190","description":"github.com \u6ce2\u5f62\u3092\u53d6\u5f97\u3059\u308b\u305f\u3081\u306b\u306f\u3001\u30d3\u30eb\u30c9\u6642\u306btrace=1\u3092\u6307\u5b9a\u3059\u308b\u5fc5\u8981\u304c\u3042\u308b\u3002 cd hardware make verilate trace=1 \u30b7\u30df\u30e5\u30ec\u30fc\u30b7\u30e7\u30f3\u306e\u5b9f\u884c\u65b9\u6cd5\u306f\u4ee5\u4e0b\u3002 app=rv64uv-ara-vle8 make simv trace=1 \u4ee5\u4e0b\u306e\u30d5\u30a1\u30a4\u30eb\u304c\u751f\u6210\u3055\u308c\u308b\u3002 trace_hart_00.dasm sim.fst spike-dasm < trace_hart_00.dasm | less 1844 0x8000012a U (0x0000e426) c.sdsp s1, 8(sp) 1844 0x8000012c U (0x0000453d) c.l\u2026","published":"2023-05-10 04:00:00","url":"https://msyksphinz.hatenablog.com/entry/2023/05/10/040000","blog_title":"FPGA\u958b\u767a\u65e5\u8a18","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmsyksphinz.hatenablog.com%2Fentry%2F2023%2F05%2F10%2F040000\" title=\"RISC-V Vector 1.0 \u3092\u30b5\u30dd\u30fc\u30c8\u3059\u308b\u30aa\u30fc\u30d7\u30f3\u30bd\u30fc\u30b9CPU Ara\u3092\u8a66\u3059 (2. \u6ce2\u5f62\u306e\u53d6\u5f97\u65b9\u6cd5) - FPGA\u958b\u767a\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","type":"rich","version":"1.0"}