{"height":"190","blog_url":"https://msyksphinz.hatenablog.com/","url":"https://msyksphinz.hatenablog.com/entry/2023/06/02/040000","published":"2023-06-02 04:00:00","author_url":"https://blog.hatena.ne.jp/msyksphinz/","blog_title":"FPGA\u958b\u767a\u65e5\u8a18","title":"RISC-V Vectorized FFTW3\u3092\u8a66\u3059 (3. Clang\u3092\u4f7f\u3063\u3066\u30d3\u30eb\u30c9)","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmsyksphinz.hatenablog.com%2Fentry%2F2023%2F06%2F02%2F040000\" title=\"RISC-V Vectorized FFTW3\u3092\u8a66\u3059 (3. Clang\u3092\u4f7f\u3063\u3066\u30d3\u30eb\u30c9) - FPGA\u958b\u767a\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","description":"FFTW3\u306e\u30d3\u30eb\u30c9\u3092\u3044\u308d\u3044\u308d\u8a66\u884c\u3057\u3066\u3044\u308b\u3002\u3068\u308a\u3042\u3048\u305aC\u62e1\u5f35\u3092\u4f7f\u3044\u305f\u304f\u306a\u3044\u306e\u3060\u304c\u3001GCC\u306fC\u3092\u9664\u3044\u305f\u30b3\u30f3\u30d1\u30a4\u30eb\u3092\u3057\u3066\u304f\u308c\u306a\u3044\u3002 Clang\u306a\u3089\u3070\u884c\u3051\u308b\u6c17\u304c\u3057\u305f\u306e\u3067\u3001\u8a66\u3057\u3066\u307f\u305f\u3002 git clone https://github.com/sh-zheng/fftw3.git fftw3-zheng cd fftw3-zheng ./bootstrap.sh --host=riscv64-unknown-elf --disable-threads ./configure --enable-maintainer-mode --enable-rvv --host=riscv64-unknown-elf \u2026","width":"100%","provider_name":"Hatena Blog","author_name":"msyksphinz","provider_url":"https://hatena.blog","image_url":null,"version":"1.0","categories":[],"type":"rich"}