{"version":"1.0","blog_url":"https://msyksphinz.hatenablog.com/","url":"https://msyksphinz.hatenablog.com/entry/2023/12/26/040000_1","width":"100%","provider_name":"Hatena Blog","author_url":"https://blog.hatena.ne.jp/msyksphinz/","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmsyksphinz.hatenablog.com%2Fentry%2F2023%2F12%2F26%2F040000_1\" title=\"LiteX 2023.12 \u30ea\u30ea\u30fc\u30b9\u78ba\u8a8d - FPGA\u958b\u767a\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","type":"rich","categories":[],"image_url":null,"published":"2023-12-26 04:00:00","provider_url":"https://hatena.blog","title":"LiteX 2023.12 \u30ea\u30ea\u30fc\u30b9\u78ba\u8a8d","author_name":"msyksphinz","height":"190","description":"CHANGES\u306f\u4ee5\u4e0b\u306e\u901a\u308a\u3002\u3053\u308c\u3092\u898b\u308b\u9650\u308a\u3042\u307e\u308a\u5927\u304d\u306a\u5909\u66f4\u306f\u306a\u3044\u3088\u3046\u306b\u601d\u3048\u308b\u3002 \u81ea\u5206\u306e\u81ea\u4f5cCPU\u3092\u30a2\u30c3\u30d7\u30c7\u30fc\u30c8\u3057\u3066\u3001\u8a66\u3057\u3066\u307f\u306a\u3051\u308c\u3070\u3002 [> Fixed -------- - liteeth/arp : Fixed response on table update. - litesata/us(p)sataphy : Fixed data_width=32 case. - clock/lattice_ecp5 : Fixed phase calculation. - interconnect/axi : Fixed AXILite2CSR read access (1 CSR cycle in\u2026","blog_title":"FPGA\u958b\u767a\u65e5\u8a18"}