{"blog_title":"FPGA\u958b\u767a\u65e5\u8a18","width":"100%","provider_name":"Hatena Blog","image_url":null,"blog_url":"https://msyksphinz.hatenablog.com/","categories":[],"author_url":"https://blog.hatena.ne.jp/msyksphinz/","published":"2024-04-15 04:00:00","title":"Spike\u306ePLIC\u3068CLINT\u306e\u5b9f\u88c5\u3092\u78ba\u8a8d\u3059\u308b","provider_url":"https://hatena.blog","height":"190","url":"https://msyksphinz.hatenablog.com/entry/2024/04/15/040000","description":"\u524d\u56de\u306e\u7d9a\u304d\u3002exception interrupt #7\u3068\u3044\u3046\u306e\u306f\u4f8b\u5916\u304b\u3068\u601d\u3063\u3066\u3044\u305f\u3089\u5272\u308a\u8fbc\u307f\u3060\u3063\u305f\u3002 \u3064\u307e\u308a\u3001\u3053\u306e\u5272\u308a\u8fbc\u307f\u304c\u5165\u3063\u305f\u6642\u70b9\u3067\u30bf\u30a4\u30de\u5272\u308a\u8fbc\u307f\u304c\u639b\u304b\u3063\u3066\u3044\u305f\u3053\u3068\u304c\u308f\u304b\u308b\u3002 \u30bf\u30a4\u30de\u5272\u308a\u8fbc\u307f\u306fCLINT\u304c\u884c\u3046\u306f\u305a\u306a\u306e\u3067\u3001\u305d\u306e\u8fba\u3092\u78ba\u8a8d\u3057\u3066\u307f\u308b\u3002 core 0: 3 0x0000000000002b2c (0x01851863) core 0: 0x0000000000002b3c (0x00813583) ld a1, 8(sp) core 0: 3 0x0000000000002b3c (0x00813583) x11 0x00000000100001c0 mem 0x000000001\u2026","author_name":"msyksphinz","type":"rich","version":"1.0","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmsyksphinz.hatenablog.com%2Fentry%2F2024%2F04%2F15%2F040000\" title=\"Spike\u306ePLIC\u3068CLINT\u306e\u5b9f\u88c5\u3092\u78ba\u8a8d\u3059\u308b - FPGA\u958b\u767a\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>"}