{"provider_name":"Hatena Blog","image_url":null,"description":"RTL\u3092\u66f8\u304f\u3068\u304d\u306fverilog-mode\u3092\u4f7f\u3063\u3066\u304d\u305f\u304c\u3001indent\u304c\u5408\u308f\u306a\u3044\u3001\u81ea\u5206\u3067typedef\u3057\u305f\u578b\u306b\u8272\u304c\u4ed8\u304b\u306a\u3044\u3001\u66f8\u304d\u9593\u9055\u3048\u3066\u3082Verilator\u3092\u56de\u3059\u307e\u3067\u6c17\u4ed8\u304b\u306a\u3044\u3001\u3068\u3044\u3046\u4e0d\u6e80\u304c\u6e9c\u307e\u3063\u3066\u3044\u305f\u3002 \u4eca\u56de\u306fEmacs Lisp\u3060\u3051\u3067lexer\u3068parser\u3092\u66f8\u304d\u3001\u305d\u306e\u4e0a\u306bhighlight\u3068indent\u3092\u8f09\u305b\u308b\u3068\u3053\u308d\u307e\u3067\u306e\u8a18\u9332\u3002 lint\u3001formatter\u3001rename\u3001\u968e\u5c64browser\u306f\u6b21\u56de\u306b\u56de\u3059\u3002 \u7d50\u679c\u3068\u3057\u3066Elisp 6312\u884c\u3001ERT test 124\u672c\u306b\u306a\u308a\u3001PULP\u306eaxi\u3068common_cells (225 file / 314 design unit) \u306b\u5bfe\u3057\u3066par\u2026","blog_title":"FPGA\u958b\u767a\u65e5\u8a18","published":"2026-09-22 04:00:00","height":"190","blog_url":"https://msyksphinz.hatenablog.com/","provider_url":"https://hatena.blog","categories":[],"width":"100%","author_name":"msyksphinz","type":"rich","version":"1.0","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fmsyksphinz.hatenablog.com%2Fentry%2F2026%2F09%2F22%2F040000\" title=\"Emacs\u306eSystemVerilog\u74b0\u5883\u3092\u81ea\u4f5c\u3059\u308b (1. lexer\u3068parser\u3001highlight\u3068indent) - FPGA\u958b\u767a\u65e5\u8a18\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","url":"https://msyksphinz.hatenablog.com/entry/2026/09/22/040000","title":"Emacs\u306eSystemVerilog\u74b0\u5883\u3092\u81ea\u4f5c\u3059\u308b (1. lexer\u3068parser\u3001highlight\u3068indent)","author_url":"https://blog.hatena.ne.jp/msyksphinz/"}