{"categories":["FPGA \u7248 FM \u97f3\u6e90"],"version":"1.0","width":"100%","published":"2010-12-15 18:28:52","type":"rich","provider_url":"https://hatena.blog","height":"190","image_url":null,"provider_name":"Hatena Blog","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fpcm1723.hateblo.jp%2Fentry%2F20101215%2F1292405332\" title=\" FPGA \u7248 FM \u97f3\u6e90 (5) -- EG (2) - \u30b7\u30f3\u30bb\u30fb\u30a2\u30f3\u30d7\u30e9\u30b0\u30c9\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","url":"https://pcm1723.hateblo.jp/entry/20101215/1292405332","blog_title":"\u30b7\u30f3\u30bb\u30fb\u30a2\u30f3\u30d7\u30e9\u30b0\u30c9","author_name":"pcm1723","description":"\u524d\u56de\u306e\u8a18\u4e8b\u3067\u8ff0\u3079\u305f\u3001 Windows 98 \u306e MS-DOS \u30b3\u30de\u30f3\u30c9\u30fb\u30d7\u30ed\u30f3\u30d7\u30c8\u4e0a\u306e DOS \u7248 FM \u97f3\u8272\u30a8\u30c7\u30a3\u30bf\u3067\u64cd\u4f5c S/PDIF \u7d4c\u7531\u3067\u5225 PC \u3067\u6ce2\u5f62\u30ad\u30e3\u30d7\u30c1\u30e3 \u6642\u9593\u8ef8\u53cd\u8ee2\u304a\u3088\u3073\u51e6\u7406 \u3068\u3044\u3046\u624b\u9806\u3067\u6c42\u3081\u305f\u3001RR (Release Rate) \u3092 1 \u304b\u3089 3 \u307e\u3067\u5909\u3048\u3066\u30d7\u30ed\u30c3\u30c8\u3057\u305f\u7d50\u679c\u3092\u4e0b\u306b\u793a\u3057\u307e\u3059\u3002","author_url":"https://blog.hatena.ne.jp/pcm1723/","title":" FPGA \u7248 FM \u97f3\u6e90 (5) -- EG (2)","blog_url":"https://pcm1723.hateblo.jp/"}