{"provider_url":"https://hatena.blog","blog_title":"\u30b7\u30f3\u30bb\u30fb\u30a2\u30f3\u30d7\u30e9\u30b0\u30c9","type":"rich","author_url":"https://blog.hatena.ne.jp/pcm1723/","title":"PSoC Creator \u306e Verilog-HDL \u306e\u30ea\u30c0\u30af\u30b7\u30e7\u30f3\u6f14\u7b97\u306e\u4e0d\u5177\u5408 (1)","url":"https://pcm1723.hateblo.jp/entry/2020/03/25/171828","blog_url":"https://pcm1723.hateblo.jp/","description":"PSoC Creator \u306e\u30e6\u30fc\u30b6\u30fb\u30b3\u30f3\u30dd\u30fc\u30cd\u30f3\u30c8\u3068\u3057\u3066\u3001(LS)TTL / HCMOS \u306e 4 \u30d3\u30c3\u30c8 ALU \u3067\u3042\u308b 74181 \u306e\u5185\u90e8\u56de\u8def\u3092 Verilog-HDL \u3067\u66f8\u3044\u3066\u3044\u3066\u3001\u300c\u30ea\u30c0\u30af\u30b7\u30e7\u30f3\u6f14\u7b97\u300d\u306b\u95a2\u3059\u308b\u4e0d\u5177\u5408\u304c\u3042\u308b\u3053\u3068\u306b\u6c17\u304c\u4ed8\u304d\u307e\u3057\u305f\u3002 \u56de\u907f\u3059\u308b\u65b9\u6cd5\u3082\u5224\u660e\u3057\u3066\u3044\u308b\u306e\u3067\u3001\u5b9f\u7528\u4e0a\u306f\u554f\u984c\u3042\u308a\u307e\u305b\u3093\u3002","height":"190","author_name":"pcm1723","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fpcm1723.hateblo.jp%2Fentry%2F2020%2F03%2F25%2F171828\" title=\"PSoC Creator \u306e Verilog-HDL \u306e\u30ea\u30c0\u30af\u30b7\u30e7\u30f3\u6f14\u7b97\u306e\u4e0d\u5177\u5408 (1) - \u30b7\u30f3\u30bb\u30fb\u30a2\u30f3\u30d7\u30e9\u30b0\u30c9\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","categories":["PSoC5LP","Verilog-HDL","UDB"],"width":"100%","published":"2020-03-25 17:18:28","provider_name":"Hatena Blog","version":"1.0","image_url":null}