{"provider_url":"https://hatena.blog","type":"rich","width":"100%","author_name":"shuzo_kino","published":"2018-05-01 23:53:08","url":"https://shuzo-kino.hateblo.jp/entry/2018/05/01/235308","blog_title":"Bye Bye Moore","blog_url":"https://shuzo-kino.hateblo.jp/","description":"shuzo-kino.hateblo.jp \u30b7\u30ea\u30fc\u30ba\u306e\uff14\u3001\u4eca\u56de\u306f\u81ea\u524d\u306eHDL\u3067L\u30c1\u30ab\u3057\u3066\u307f\u307e\u3059\u3002 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity WebPack_QuickStart is Port ( A : out STD_LOGIC_VECTOR (15 downto 0); B : out STD_LOGIC_VECTOR (15 downto 0); C : out STD_LOGIC_VECTOR (15 \u2026","version":"1.0","image_url":null,"height":"190","title":"FPGA\u30dc\u30fc\u30c9Papillo ONE\u3067\u3042\u305d\u3076\u3000\u305d\u306e\uff14\uff1a\u81ea\u524dHDL\u3067L\u30c1\u30ab","provider_name":"Hatena Blog","categories":["fpga"],"html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fshuzo-kino.hateblo.jp%2Fentry%2F2018%2F05%2F01%2F235308\" title=\"FPGA\u30dc\u30fc\u30c9Papillo ONE\u3067\u3042\u305d\u3076\u3000\u305d\u306e\uff14\uff1a\u81ea\u524dHDL\u3067L\u30c1\u30ab - Bye Bye Moore\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","author_url":"https://blog.hatena.ne.jp/shuzo_kino/"}