{"image_url":null,"height":"190","blog_url":"https://shuzo-kino.hateblo.jp/","provider_url":"https://hatena.blog","version":"1.0","author_url":"https://blog.hatena.ne.jp/shuzo_kino/","title":"\u30d0\u30b9\u3092\u7e4b\u3050&\u6f14\u7b97\u5b50\uff20VHDL","provider_name":"Hatena Blog","categories":["fpga"],"url":"https://shuzo-kino.hateblo.jp/entry/2018/05/02/232339","author_name":"shuzo_kino","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fshuzo-kino.hateblo.jp%2Fentry%2F2018%2F05%2F02%2F232339\" title=\"\u30d0\u30b9\u3092\u7e4b\u3050&amp;\u6f14\u7b97\u5b50\uff20VHDL - Bye Bye Moore\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","published":"2018-05-02 23:23:39","type":"rich","blog_title":"Bye Bye Moore","width":"100%","description":"VHDL\u3067FPGA\u3067\u30d0\u30b9\u3092\u7e4b\u3050\u306b\u306f\"&\u6f14\u7b97\u5b50\"\u3092\u3064\u304b\u3044\u307e\u3059 \u5b9f\u969b\u306e\u3068\u3053\u308d library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Switches_LEDs is Port ( switches : in STD_LOGIC_VECTOR(1 downto 0); LEDs : out STD_LOGIC_VECTOR(1 downto 0)); end Switches_LEDs; begin LEDs <= switches; end Behavioral; switches(0)\u304c'1'\u3001switches(1)\u304c'0'\u306e\u3068\u304d\u3001\u3053\u308c\u3089\u306f\u540c\u3058\u610f\u5473\u3067\u2026"}