{"author_name":"shuzo_kino","provider_name":"Hatena Blog","categories":["fpga"],"provider_url":"https://hatena.blog","description":"count: process(clock) begin if rising_edge(clock) then if switch1 = \u20191\u2019 then if switch2 = \u20191\u2019 then output_signal <= \u20191\u2019; else output_signal <= \u20190\u2019; end if; end if; end if; end process; \u53c2\u8003\u3082\u3068 https://cdn.sparkfun.com/datasheets/Dev/FPGA/IntroToSpartanFPGABook.pdf","width":"100%","url":"https://shuzo-kino.hateblo.jp/entry/2018/05/03/235452","type":"rich","title":"VHDL\u306b\u304a\u3051\u308bIF\u6587","image_url":null,"published":"2018-05-03 23:54:52","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fshuzo-kino.hateblo.jp%2Fentry%2F2018%2F05%2F03%2F235452\" title=\"VHDL\u306b\u304a\u3051\u308bIF\u6587 - Bye Bye Moore\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","version":"1.0","blog_url":"https://shuzo-kino.hateblo.jp/","height":"190","blog_title":"Bye Bye Moore","author_url":"https://blog.hatena.ne.jp/shuzo_kino/"}