{"type":"rich","provider_url":"https://hatena.blog","author_name":"shuzo_kino","image_url":null,"provider_name":"Hatena Blog","url":"https://shuzo-kino.hateblo.jp/entry/2018/05/04/235346","title":"VHDL\u306e\u30e2\u30b8\u30e5\u30fc\u30eb\u5b9a\u7fa9","categories":["fpga"],"published":"2018-05-04 23:53:46","height":"190","version":"1.0","width":"100%","blog_url":"https://shuzo-kino.hateblo.jp/","blog_title":"Bye Bye Moore","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fshuzo-kino.hateblo.jp%2Fentry%2F2018%2F05%2F04%2F235346\" title=\"VHDL\u306e\u30e2\u30b8\u30e5\u30fc\u30eb\u5b9a\u7fa9 - Bye Bye Moore\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","description":"entity\u3001architecture\u306a\u3069VHDL\u306b\u306f\u8272\u3005\u30e2\u30b8\u30e5\u30fc\u30eb\u5b9a\u7fa9\u304c\u3042\u308a\u307e\u3059\u3002 \u4eca\u56de\u306f\u30b3\u30ec\u306e\u79c1\u7684\u307e\u3068\u3081\u3067\u3059 \u5b9f\u969b\u306e\u3068\u3053\u308d \u5185\u90e8\u7684\u306a\u30e2\u30b8\u30e5\u30fc\u30eb\u304centity entity mymodule is Port ( input1 : in STD_LOGIC_VECTOR (3 downto 0); output1 : out STD_LOGIC_VECTOR (3 downto 0)); end mymodule; entity\u3092\u3046\u3051\u3066\u3001\u632f\u308b\u821e\u3044\u3092\u5b9a\u7fa9\u3059\u308b\u306e\u304carchitecture architecture Behavioral of mymodule is begin output1 <=\u2026","author_url":"https://blog.hatena.ne.jp/shuzo_kino/"}