{"title":"Intel NNP-T\u306e\u30b5\u30fc\u30d0\u30fc","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F2019%2F12%2F25%2F060000\" title=\"Intel NNP-T\u306e\u30b5\u30fc\u30d0\u30fc - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","url":"https://vengineer.hatenablog.com/entry/2019/12/25/060000","width":"100%","provider_name":"Hatena Blog","type":"rich","published":"2019-12-25 06:00:00","description":"@Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f Intel \u304c Habana Labs\u3092\u8cb7\u53ce\u3059\u308b\u3068\u3044\u3046\u5642\u306b\u95a2\u3057\u3066\u306f\u3001\u6628\u65e5\u306e\u30d6\u30ed\u30b0\u306b\u66f8\u304d\u307e\u3057\u305f\u304c\u3001Intel \u304c \u305d\u306e\u524d\u306b\u8cb7\u53ce\u3057\u305f Nervana \u306e NNP-I \u3068 NNP-T \u306e\u60c5\u5831\u3002 fuse.wikichip.org \u3053\u306e\u8a18\u4e8b\u306e\u4e2d\u3067\u3001 Supermicro at its booth at Supercomputing 2019. Supermicro first NNP-T system features two Cascade Lake CPU\u2026","height":"190","provider_url":"https://hatena.blog","blog_url":"https://vengineer.hatenablog.com/","author_name":"Vengineer","image_url":"https://fuse.wikichip.org/wp-content/uploads/2019/12/sc19-supermicro-nnpt-pcie.jpg","version":"1.0","author_url":"https://blog.hatena.ne.jp/Vengineer/","categories":[],"blog_title":"Vengineer\u306e\u5984\u60f3"}