{"version":"1.0","author_name":"Vengineer","blog_title":"Vengineer\u306e\u5984\u60f3","width":"100%","blog_url":"https://vengineer.hatenablog.com/","provider_url":"https://hatena.blog","image_url":null,"author_url":"https://blog.hatena.ne.jp/Vengineer/","title":"SV/UVM based instruction generator for RISC-V processor verification","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F2020%2F02%2F08%2F060000\" title=\"SV/UVM based instruction generator for RISC-V processor verification - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","type":"rich","provider_name":"Hatena Blog","url":"https://vengineer.hatenablog.com/entry/2020/02/08/060000","categories":[],"published":"2020-02-08 06:00:00","description":"@Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f \u898b\u3064\u3051\u305f\u3002 github.com \u305f\u3060\u3057\u3001\u304a\u9ad8\u3044\u30b7\u30df\u30e5\u30ec\u30fc\u30bf\u304c\u5fc5\u8981\u3002 To be able to run the instruction generator, you need to have an RTL simulator which supports SystemVerilog and UVM 1.2. This generator has been verified with Synopsys VCS, Cadence Incisive/Xce\u2026","height":"190"}