{"title":"Xilinx QEMU + SystemC (PCIe EP) + Verilog HDL (Verilator) \u306e\u5185\u5bb9\u3092\u63a2\u3063\u3066\u3044\u304f(\u305d\u306e2)","url":"https://vengineer.hatenablog.com/entry/2021/04/08/100000","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F2021%2F04%2F08%2F100000\" title=\"Xilinx QEMU + SystemC (PCIe EP) + Verilog HDL (Verilator) \u306e\u5185\u5bb9\u3092\u63a2\u3063\u3066\u3044\u304f(\u305d\u306e2) - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","height":"190","description":"@Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f \u306f\u3058\u3081\u306b Xilinx QEMU + SystemC (PCIe EP) \u306e\u5185\u5bb9\u3092\u63a2\u3063\u3066\u3044\u304f(\u305d\u306e1) \u3067\u8aac\u660e\u3057\u305f\u3001refdesign-sim.cc \u306e\u30d6\u30ed\u30c3\u30af\u56f3\u306f\u4e0b\u8a18\u306e\u3088\u3046\u306b\u306a\u3063\u3066\u3044\u307e\u3059\u3002QEMU\u3068\u306e\u901a\u4fe1\u306f\u3001remoteport_tlm_pci_ep \u304c\u884c\u3063\u3066\u3044\u307e\u3059\u3002\u3053\u306e remoteport_tlm_pcie_ep \u306b\u3001xilinx_xdma \u304c\u63a5\u7d9a\u3057\u3066\u3044\u3066\u3001\u305d\u306e\u5148\u306b\u3001iconnect (xdma_ic)\u304c\u3042\u3063\u3066\u3001tlm=>axi bridge \u3092\u2026","blog_title":"Vengineer\u306e\u5984\u60f3","author_url":"https://blog.hatena.ne.jp/Vengineer/","version":"1.0","provider_name":"Hatena Blog","blog_url":"https://vengineer.hatenablog.com/","categories":[],"image_url":"https://cdn-ak.f.st-hatena.com/images/fotolife/V/Vengineer/20210404/20210404112657.png","author_name":"Vengineer","provider_url":"https://hatena.blog","width":"100%","published":"2021-04-08 10:00:00","type":"rich"}