{"image_url":null,"height":"190","provider_name":"Hatena Blog","provider_url":"https://hatena.blog","version":"1.0","url":"https://vengineer.hatenablog.com/entry/2021/05/20/090000","type":"rich","blog_title":"Vengineer\u306e\u5984\u60f3","title":"Dynamic Scheduler\u7248\u306eVerilator\u306e\u4e2d\u3092\u8abf\u3079\u308b(\u305d\u306e2)","width":"100%","blog_url":"https://vengineer.hatenablog.com/","author_name":"Vengineer","published":"2021-05-20 09:00:00","description":"@Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f \u306f\u3058\u3081\u306b Dynamic Scheduler\u7248 Verilator\u306e\u4e2d\u3092\u8abf\u3079\u308b\u3001\u305d\u306e2\u3002\u4eca\u56de\u306f\u3001events (-> \u3084 @event) \u304c\u3069\u306e\u3088\u3046\u306b\u5b9f\u88c5\u3055\u308c\u3066\u3044\u308b\u304b\u3092\u8abf\u3079\u3066\u3044\u304d\u307e\u3059\u3002 Verilog HDL\u30b3\u30fc\u30c9 Verilog HDL\u30b3\u30fc\u30c9 (examples/events.v) \u3092\u4ee5\u4e0b\u306b\u793a\u3057\u307e\u3059\u3002event \u304c\u305f\u304f\u3055\u3093\u3042\u308a\u307e\u3059\u3002 always @(posedge clk) \u30d6\u30ed\u30c3\u30af\u306e\u4e2d initial \u6587 @(event) \u306e3\u7a2e\u985e\u3067\u306e\u30c6\u30b9\u30c8\u30b3\u30fc\u2026","categories":[],"author_url":"https://blog.hatena.ne.jp/Vengineer/","html":""}