{"version":"1.0","blog_title":"Vengineer\u306e\u5984\u60f3","author_name":"Vengineer","provider_url":"https://hatena.blog","title":"UHDM \u3068 UHDM-Verilator Integration\u306e\u30d3\u30eb\u30c9","type":"rich","description":"@Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f \u306f\u3058\u3081\u306b ASIC \u3084 FPGA \u306e\u958b\u767a\u306b\u3082\u4e0b\u8a18\u306e\u3088\u3046\u306a\u30aa\u30fc\u30d7\u30f3\u30bd\u30fc\u30b9\u306e\u30bd\u30d5\u30c8\u30a6\u30a7\u30a2\u3092\u4f7f\u3046\u52d5\u304d\u304c\u6d3b\u767a\u306b\u306a\u3063\u3066\u304d\u307e\u3057\u305f\u3002 Yosys Open SYnthesis Suite : \u8ad6\u7406\u5408\u6210\u30c4\u30fc\u30eb(Verilog HDL 2005)\u3001Xilinx 7-Series, Lattece iCE40 Verilator : Verilog HDL/SystemVerilog Simulator VTR : Verilog to Route : FPGA\u7528\u958b\u767a\u30c4\u30fc\u2026","published":"2021-07-19 09:00:00","author_url":"https://blog.hatena.ne.jp/Vengineer/","provider_name":"Hatena Blog","width":"100%","blog_url":"https://vengineer.hatenablog.com/","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F2021%2F07%2F19%2F090000\" title=\"UHDM \u3068 UHDM-Verilator Integration\u306e\u30d3\u30eb\u30c9 - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","height":"190","image_url":null,"url":"https://vengineer.hatenablog.com/entry/2021/07/19/090000","categories":[]}