{"categories":[],"provider_name":"Hatena Blog","width":"100%","blog_url":"https://vengineer.hatenablog.com/","height":"190","type":"rich","provider_url":"https://hatena.blog","published":"2021-12-20 09:00:00","url":"https://vengineer.hatenablog.com/entry/2021/12/20/090000","blog_title":"Vengineer\u306e\u5984\u60f3","version":"1.0","image_url":"https://cdn-ak.f.st-hatena.com/images/fotolife/V/Vengineer/20211215/20211215161423.png","author_url":"https://blog.hatena.ne.jp/Vengineer/","title":"SiliconCompiler\u306e\u30c7\u30e2\u3067\u3042\u308bZeroSoC\u3092\u30d3\u30eb\u30c9\u3057\u3066\u307f\u305f","description":"\u306f\u3058\u3081\u306b SiliconCompiler\u306e\u30c7\u30e2\u3068\u3057\u3066\u306e ZeroSoC\u306e\u30d3\u30eb\u30c9\u3092\u30c8\u30e9\u30a4\u30a2\u30eb\u3057\u307e\u3057\u305f\u3002 ZeroSoC consists of an Ibex core, UART and GPIO peripherals from the OpenTitan project, and 8 KB of RAM. SIlicomCompiler\u306e\u4ed6\u306b\u3001 magic netgen sv2v : SystemVerilog \u306e\u8a18\u8ff0\u3092 Verilog HDL \u306e\u8a18\u8ff0\u306b\u5909\u63db\u3059\u308b \u304c\u5fc5\u8981\u306e\u3088\u3046\u3067\u3059\u3002 Magic VLSI (magic) csh \u304c\u5fc5\u8981\u306a\u306e\u3067\u3001\"sudo apt install csh\" \u3067\u2026","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F2021%2F12%2F20%2F090000\" title=\"SiliconCompiler\u306e\u30c7\u30e2\u3067\u3042\u308bZeroSoC\u3092\u30d3\u30eb\u30c9\u3057\u3066\u307f\u305f - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","author_name":"Vengineer"}