{"categories":[],"provider_name":"Hatena Blog","height":"190","author_url":"https://blog.hatena.ne.jp/Vengineer/","width":"100%","title":"2021\u5e74\u3092\u632f\u308a\u8fd4\u3063\u3066","image_url":null,"version":"1.0","blog_url":"https://vengineer.hatenablog.com/","blog_title":"Vengineer\u306e\u5984\u60f3","description":"\u306f\u3058\u3081\u306b \u307e\u305a\u306f\u30012021\u5e741\u67081\u65e5\u306e\u30d6\u30ed\u30b0\u3092\u632f\u308a\u8fd4\u3063\u3066\u307f\u307e\u3059\u3002 vengineer.hatenablog.com \u8b1b\u6f14\u30d3\u30c7\u30aa\u3092\u898b\u3066\u3001\u30d6\u30ed\u30b0\u306b\u66f8\u3044\u305f\u306e\u3063\u3066\u30011\u6708\u304b\u30893\u6708\u307e\u3067\u3060\u3051\u3060\u3063\u305f\u6c17\u304c\u3057\u307e\u3059\u3002 2021\u5e74\u3092\u632f\u308a\u8fd4\u3063\u3066\u307f\u308b 1\u6708\u30012\u6708\u306f\u3001Apple M1\u95a2\u9023\u304c\u591a\u304b\u3063\u305f\u3067\u3059\u3002 3\u6708\u306f\u3001Xilinx\u306eQEMU + SystemC + Verilog HDL (Verilator) \u306e\u30c7\u30e2\u306e\u5185\u5bb9\u3092\u63a2\u3063\u3066\u3044\u304f\u3001\u305f\u308a\u3057\u3066\u3044\u305f\u3002 4\u6708\u30015\u6708\u306f\u3001Verilator\u306b\u3064\u3044\u3066\u8abf\u3079\u3066\u3044\u305f 7\u6708\u306f\u3001\u4ffa\u69d8FPGA\u306e\u304a\u8a71\u3002 8\u6708\u304b\u308910\u6708\u306f\u3001\u96d1\u8ac7\u30011on1\u3001\u534a\u5c0e\u4f53\u30c1\u30c3\u30d7\u96d1\u8ac7\u3092\u3084\u3063\u3066\u3044\u307e\u3057\u305f\u3002 12\u6708\u306f\u3001SiliconC\u2026","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F2021%2F12%2F31%2F060000\" title=\"2021\u5e74\u3092\u632f\u308a\u8fd4\u3063\u3066 - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","url":"https://vengineer.hatenablog.com/entry/2021/12/31/060000","author_name":"Vengineer","published":"2021-12-31 06:00:00","provider_url":"https://hatena.blog","type":"rich"}