{"image_url":"https://cdn-ak.f.st-hatena.com/images/fotolife/V/Vengineer/20220110/20220110102311.png","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F2022%2F01%2F11%2F090000\" title=\"SemiAnalysis \u306e\u8a18\u4e8b\u3092\u773a\u3081\u3066\u3044\u308b\u3068\u3001\u5b66\u3073\u3057\u304b\u306a\u3044 - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","width":"100%","description":"\u306f\u3058\u3081\u306b SimiAnalysis \u306e\u8a18\u4e8b\u3092\u773a\u3081\u3066\u3044\u308b\u3068\u3001\u5b66\u3073\u3057\u304b\u306a\u3044 SRAM\u306e\u30b9\u30b1\u30fc\u30ea\u30f3\u30b0\u306e\u304a\u8a71 TSMC N7 => N5 \u3067\u306f\u3001 Logic Area \u306f\u30011.8 X SRAM Area \u306f\u30011.35 X Analog Area \u306f\u30011.2 X \u3067\u3042\u308a\u3001SRAM\u304c\u591a\u3044\u3068\u3001\u5168\u4f53\u3068\u3057\u3066\u306f\u3042\u307e\u308a\u30b9\u30b1\u30fc\u30eb\u3057\u306a\u3044\u3068\u3044\u3046\u3053\u3068\u306b\u3002 TSMC\u306b\u3088\u308b\u3068\u3001N5 \u3067\u306f 35 - 40 \uff05 \u3050\u3089\u3044\u3002 TSMC\u3068Samsung\u3067\u306f\u30013D stacked SRAM \u3068\u3044\u3046\u30a2\u30d7\u30ed\u30fc\u30c1\u3092\u9032\u3081\u3066\u3044\u308b (AMD \u306e Milan => Milan-X : L3 Cache Stack \u4ed8)\u3063\u3066\u611f\u3058\u3067\u3059\u304b\u306d\u3002 semiana\u2026","author_name":"Vengineer","type":"rich","url":"https://vengineer.hatenablog.com/entry/2022/01/11/090000","height":"190","blog_url":"https://vengineer.hatenablog.com/","title":"SemiAnalysis \u306e\u8a18\u4e8b\u3092\u773a\u3081\u3066\u3044\u308b\u3068\u3001\u5b66\u3073\u3057\u304b\u306a\u3044","version":"1.0","provider_url":"https://hatena.blog","author_url":"https://blog.hatena.ne.jp/Vengineer/","categories":[],"published":"2022-01-11 09:00:00","provider_name":"Hatena Blog","blog_title":"Vengineer\u306e\u5984\u60f3"}