{"provider_url":"https://hatena.blog","provider_name":"Hatena Blog","image_url":null,"height":"190","title":"VHDL\u30b7\u30df\u30e5\u30ec\u30fc\u30bf nvc","width":"100%","blog_title":"Vengineer\u306e\u5984\u60f3","url":"https://vengineer.hatenablog.com/entry/2022/08/18/090000","type":"rich","version":"1.0","categories":[],"description":"\u306f\u3058\u3081\u306b @ikwzm \u3055\u3093\u306e\u3053\u306eTweet\u3067\u77e5\u3063\u305f\u3001VHDL\u30b7\u30df\u30e5\u30ec\u30fc\u30bfnvc \u30aa\u30fc\u30d7\u30f3\u30bd\u30fc\u30b9\u306a LLVM \u30d9\u30fc\u30b9\u306e VHDL \u30b7\u30df\u30e5\u30ec\u30fc\u30bf\u30fc nvc \u304c 1.7.0 \u3092\u30ea\u30ea\u30fc\u30b9\u3002\u5f53\u521d\u306f Dummy_Plug \u304c\u52d5\u304b\u306a\u304f\u3066 issue \u3092\u3042\u3052\u307e\u304f\u3063\u3066\u3044\u305f\u306e\u3060\u304c\u3001\u3053\u3053\u6700\u8fd1\u306f\u305a\u3063\u3068\u5b89\u5b9a\u52d5\u4f5c\u3057\u3066\u3044\u305f\u3002\u3055\u3063\u305d\u304f\u3001\u3044\u304f\u3064\u304b\u8a66\u3057\u3066\u307f\u3088\u3046\u3002https://t.co/nvXL2Xhrnj\u2014 \u96a0\u5c45\u3057\u305f\u30a8\u30f3\u30b8\u30cb\u30a2 (@ikwzm) 2022\u5e748\u670810\u65e5 \u3042\u305f\u3057\u306f\u3001VHDL\u64b2\u6ec5\u3057\u3066\u3082\u3089\u3044\u305f\u3044\u3068\u601d\u3063\u3066\u3044\u307e\u3059\u3002 nvc github \u306e\u3053\u3061\u3089\u3002 github.com VHDL-2002 \u3092\u30b5\u30dd\u30fc\u30c8\u3001VHDL-2008\u2026","blog_url":"https://vengineer.hatenablog.com/","published":"2022-08-18 09:00:00","author_name":"Vengineer","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F2022%2F08%2F18%2F090000\" title=\"VHDL\u30b7\u30df\u30e5\u30ec\u30fc\u30bf nvc - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","author_url":"https://blog.hatena.ne.jp/Vengineer/"}