{"provider_name":"Hatena Blog","author_name":"Vengineer","title":"Bluespec SystemVerilog \u306e\u56de\u8def\u4f8b : APB","blog_title":"Vengineer\u306e\u5984\u60f3","description":"\u306f\u3058\u3081\u306b Bluespec SystemVerilog\u3067\u5b9f\u88c5\u3055\u308c\u3066\u3044\u308b\u56de\u8def\u4f8b\u306e\u7d39\u4ecb\u3001\u4eca\u56de\u306fBluespec\u306eAPB\u3067\u3059\u3002 github.com \u30c6\u30b9\u30c8\u30d9\u30f3\u30c1 (Testbench) \u30c6\u30b9\u30c8\u30d9\u30f3\u30c1\u306f\u3001Testbench.sv \u3067\u3059\u3002 module mkTestbench (Empty); APB_Initiator_IFC source <- mkSource; APB_Target_IFC mem_model <- mkAPB_Mem_Model; mkConnection (source, mem_model); rule rl_dummy_APB_decoder_and_mux; mem_\u2026","blog_url":"https://vengineer.hatenablog.com/","image_url":null,"provider_url":"https://hatena.blog","published":"2023-09-17 08:00:00","height":"190","url":"https://vengineer.hatenablog.com/entry/2023/09/17/080000","author_url":"https://blog.hatena.ne.jp/Vengineer/","width":"100%","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F2023%2F09%2F17%2F080000\" title=\"Bluespec SystemVerilog \u306e\u56de\u8def\u4f8b : APB - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","type":"rich","version":"1.0","categories":[]}