{"width":"100%","categories":[],"author_name":"Vengineer","provider_name":"Hatena Blog","title":"Groq \u306e V2-LPU\u3092\u5984\u60f3\u3059\u308b","type":"rich","version":"1.0","image_url":"https://cdn-ak.f.st-hatena.com/images/fotolife/V/Vengineer/20240825/20240825095832.png","provider_url":"https://hatena.blog","blog_title":"Vengineer\u306e\u5984\u60f3","height":"190","url":"https://vengineer.hatenablog.com/entry/2024/08/27/080000","description":"\u306f\u3058\u3081\u306b Groq \u306e V2-LPU \u304c2025\u5e74\u306b\u51fa\u3066\u304f\u308b\u3068\u3044\u3046\u3053\u3068\u3067\u3059\u304c\u3001\u3069\u3093\u306a\u69cb\u6210\u306b\u306a\u308b\u306e\u304b\u3092\u5984\u60f3\u3057\u307e\u3059\u3002 \u305d\u308c\u3067\u306f\u3001 Let's \u5984\u60f3 DDR/LPDDR \u3042\u308b\u306e\uff1f \u3053\u306e\u8077 (Post Silicon Validation Lead) \u306b\u3001C2C, PCIe, CXL, DDRx, LPDDR controller/chips \u3068\u3044\u3046\u8a18\u8ff0\u304c\u3042\u308a\u307e\u3057\u305f\u3002\u6d88\u3048\u3061\u3083\u3046\u306e\u3067\u9b5a\u62d3\u3092\u53d6\u3063\u3066\u6b8b\u3057\u307e\u3059\u3002 Bring-up & Silicon Characterization Validation of C2C, PCIe, CXL, DDRx, LPDDR controller/chips Valid\u2026","author_url":"https://blog.hatena.ne.jp/Vengineer/","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F2024%2F08%2F27%2F080000\" title=\"Groq \u306e V2-LPU\u3092\u5984\u60f3\u3059\u308b - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","published":"2024-08-27 08:00:00","blog_url":"https://vengineer.hatenablog.com/"}