{"html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F2025%2F05%2F18%2F080000\" title=\"Terasic \u306e Atum A3 Nano (P0803)\u306f\u3001\u7a0e\u522526,000\u5186\u306aFPGA\u30dc\u30fc\u30c9 - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","blog_url":"https://vengineer.hatenablog.com/","width":"100%","provider_name":"Hatena Blog","url":"https://vengineer.hatenablog.com/entry/2025/05/18/080000","categories":[],"image_url":"https://cdn-ak.f.st-hatena.com/images/fotolife/V/Vengineer/20250517/20250517110218.png","height":"190","blog_title":"Vengineer\u306e\u5984\u60f3","version":"1.0","author_url":"https://blog.hatena.ne.jp/Vengineer/","published":"2025-05-18 08:00:00","title":"Terasic \u306e Atum A3 Nano (P0803)\u306f\u3001\u7a0e\u522526,000\u5186\u306aFPGA\u30dc\u30fc\u30c9","description":"\u306f\u3058\u3081\u306b \u3053\u3053\u6570\u5e74\u306e\u5186\u5b89\u306b\u3066\u3001FPGA\u30dc\u30fc\u30c9\u306e\u304a\u5024\u6bb5\u304c\u30d0\u30ab\u9ad8\u304f\u306a\u3063\u3066\u3044\u307e\u3059\u3002105\u5186\u3050\u3089\u3044\u304b\u3089150-160\u5186\u306b\u306a\u3063\u305f\u306e\u3067\u30011.5\u500d\u3050\u3089\u3044\u306b\u306f\u306a\u3063\u3066\u3044\u308b\u3093\u3067\u3057\u3087\u3046\u304b\uff1f \u305d\u3093\u306a\u3001\u304a\u9ad8\u304f\u306a\u3063\u3066\u3044\u308bFPGA\u30dc\u30fc\u30c9\u3067\u3059\u304c\u3001\u4e0b\u8a18\u306e\u7acb\u91ce\u96fb\u8133\u3055\u3093\u306eX\u306e\u6295\u7a3f\u3067\u3001Atum A3 Nano \u306a\u308b\u30dc\u30fc\u30c9\u304c\u7d39\u4ecb\u3055\u308c\u3066\u3044\u307e\u3057\u305f\u3002 Atum A3 Nano (P0803) is a Terasic's new FPGA board with Intel/altera Agilex3 A3CZ135BB18AE7S.\u2014 Tateno Dennou (@TatenoDennou) 2025\u5e745\u670816\u65e5 \u304a\u5024\u6bb5\u898b\u305f\u3089\u3001\u5927\u5b66\u7b49\u7814\u2026","type":"rich","provider_url":"https://hatena.blog","author_name":"Vengineer"}