{"description":"Verification Engineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f UVM 1.0\u3067\u306f\u3001Register Package\u306e\u6a19\u6e96\u5316\u3092\u9032\u3081\u3066\u3044\u307e\u3059\u3002 3\u793e(Synopsys\u3001Cadence\u3001Mentor)\u3001\u305d\u308c\u305e\u308cRegister Package\u3092\u6301\u3063\u3066\u3044\u307e\u3059\u3002 \u4eca\u56de\u3001Open Technical Presentation on RAL based Register Package Candidate for UVM 1.0\u3068\u3044\u3046\u3082\u306e\u304c\u3001 9/8(\u6c34)\u30018:00 am(Pacific Daylight\u2026","image_url":null,"author_name":"Vengineer","height":"190","blog_url":"https://vengineer.hatenablog.com/","provider_url":"https://hatena.blog","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F62624533\" title=\"RAL\u3068UVM 1.0 - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","type":"rich","url":"https://vengineer.hatenablog.com/entry/62624533","width":"100%","version":"1.0","provider_name":"Hatena Blog","title":"RAL\u3068UVM 1.0","blog_title":"Vengineer\u306e\u5984\u60f3","author_url":"https://blog.hatena.ne.jp/Vengineer/","categories":["UVM","#\u6280\u8853\u8077"],"published":"2010-09-07 20:51:43"}