{"author_name":"Vengineer","description":"Verification Engineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f UVM 1.0\u3067TLM 2.0\u304c\u5b9f\u88c5\u3055\u308c\u307e\u3059\u304c\u3001\u305f\u3076\u3093\u3001VMM\u3092\u30d9\u30fc\u30b9\u306b\u3057\u3066\u3044\u308b\u306e\u3060\u3068\u601d\u3044\u307e\u3059\u3002 \u305d\u3053\u3067\u3001Verilab\u306e\u30b5\u30a4\u30c8\u306b\u3042\u308bInteroperable testtbenches using VMM TLM\u3092\u30c1\u30a7\u30c3\u30af\u3057\u3066\u307f\u307e\u3057\u3087\u3046\uff01 SNUG\u3067\u767a\u8868\u3055\u308c\u305f\u3082\u306e\u3067\u3001Verilab\u3068Synopsys\u306e\u5171\u8457\u3067\u3059\u3002 VMM 1.2\u306eTLM\u3060\u3051\u3067\u306a\u304f\u3001SystemC\u306eReference model\u3068\u306e\u63a5\u7d9a\u4e8b\u4f8b\u3082\u8f09\u3063\u3066\u3044\u307e\u3059\u3002 VCS\u306e\u2026","url":"https://vengineer.hatenablog.com/entry/62812367","blog_url":"https://vengineer.hatenablog.com/","published":"2010-09-29 21:00:29","blog_title":"Vengineer\u306e\u5984\u60f3","version":"1.0","categories":["VMM","#\u6280\u8853\u8077"],"author_url":"https://blog.hatena.ne.jp/Vengineer/","height":"190","type":"rich","title":"Interoperable testtbenches using VMM TLM","provider_url":"https://hatena.blog","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F62812367\" title=\"Interoperable testtbenches using VMM TLM - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","image_url":null,"provider_name":"Hatena Blog","width":"100%"}